應用於寬頻劃碼多工進接系統及無線區域網路線性補償功率放大器之研製; The Design and Implementation of Linear Compensation Power Amplifiers for W-CDMA and WLAN Applications

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題名:	應用於寬頻劃碼多工進接系統及無線區域網路線性補償功率放大器之研製;The Design and Implementation of Linear Compensation Power Amplifiers for W-CDMA and WLAN Applications
作者:	林貴城;Kuei-Cheng Lin
貢獻者:	電機工程研究所
關鍵詞:	寬頻劃碼多工進接系統;無線區域網路;矽鍺雙載子互補金屬氧化半導體;互補金屬氧化半導體製程;開汲極適應式線性放大器;預先失真;前饋式架構;適應性偏壓多帝功率放大器;變壓轉換器;SiGe BiCMOS;Predistortion;Open Adaptive Collector Bias Amplifier;Dc-Dc Converter;Adaptive Bias Doherty Amplifier;CMOS;Feedforward;W-CDMA;WLAN
日期:	2005-06-20
上傳時間:	2009-09-22 11:58:21 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	摘要本論文主題在於討論以矽製程實現高線性度之功率放大器電路，應用於寬頻劃碼多工進接系統(W-CDMA)與無線區域網路(WLAN)。採用台積電0.35?m矽鍺雙載子互補金屬氧化半導體製程及0.18?m互補金屬氧化半導體製程。以下依各章節不同的線性補償架構與應用來分類，概述論文中各電路的實際量測結果。第一章簡述相關研究及各章所描述的內容。第二章探討功率放大器必須考量的系統規格與參數，以及介紹各種不同類型的功率放大器。第三章探討開汲極適應式線性放大器應用於W-CDMA，並且找出其功率級與線性偏壓電路之間的阻抗關係藉以改善放大器的線性度，在組抗比為3的時候獲得最佳的線性改善，最後在電路加上MOS二極體使得線性補償的特性更為顯注。此電路具有13.5dB的增益、大於10dB的輸出?入回返損耗、18.6dBm的輸出1dB增益壓縮點、27.2dBm的輸出三階截斷點、31.2 %的最大功率增進效率。第四章主要在探討高線性化功率放大器應用於W-CDMA，分別有預先失真與前饋式架構兩種改善線性化的技術，一個簡單可調增益預先失真放大器能有效的降低在輸出端的三階諧波量。利用台積電製程實現簡單不複雜的預先失真電路，具有7.8dB的增益、大於10dB的輸入回返損耗、大於7dB的輸出回返損耗、17.9dBm的輸出1dB增益壓縮點、30dBm的輸出三階截斷點在可變電壓Vbep=0.9V、37%的最大功率增進效率。前饋式架構方面，以一個簡單差動對架構，適當的選擇偏壓點及元件尺寸比率來有效抑制在輸出端的三階諧波量，此電路具有7.06dB的增益、大於16dB的輸入回返損耗、大於8.5dB的輸出回返損耗、14.4 dBm的輸出1dB增益壓縮點、31dBm的輸出三階截斷點及24.5%的最大功率增進效率。第五章主要在探討高平均功率增進效率的功率放大器應用於W-CDMA及WLAN，分別有適應性偏壓多帝功率放大器與變壓轉換功率放大器兩種架構用來改善平均功率增進效率。最後利用台積電製程來實現此兩種功率放大器。量測後適應性偏壓多帝功率放大器具有6.5dB的增益、大於16dB的輸入回返損耗、大於3 dB的輸出回返損耗、20dBm的輸出1dB增益壓縮點、31dBm的輸出三階截斷點及24.5%的最大功率增進效率。變壓轉換功率放大器則具有9.5dB的增益、大於18dB的輸入回返損耗、大於5dB的輸出回返損耗、16.8dBm的輸出1dB增益壓縮點、30 dBm的輸出三階截斷點及42%的最大功率增進效率。 Abstract The thesis investigated the analysis, design and implementation of linear compensation power amplifiers with silicon-based technologies for W-CDMA, WLAN 802.11a applications. The power amplifiers were implemented in tsmc 0.35?m SiGe BiCMOS and 0.18?m CMOS technologies. The brief description of the related researches is given in the chapter one and the contents of each following chapters. In the Chapter two the specifications and the operation class of power amplifier are presented. In the Chapter three, I report a linear power amplifier with open adaptive collector biasing design for W-CDMA applications. The size effect of linearizer is investigated to improve linearity. The impedance ratio between the bias circuit and power stage is optimized at the factor of 3. Another compensated mechanism is provided by the drain-gate connected MOS diode. The diode feedback technique provides a supplement RF current in the higher power level which further enhances the linearity of the amplifier. The circuit was implemented with tsmc SiGe BiCMOS technology. This PA provides a 13.5dB gain with input or output return loss better than 10dB, and has output P1dB of 18.6dBm; output IP3 of 27.2dBm, the maximum PAE of 31.2 %. Chapter four reports a high linearity power amplifier for W-CDMA applications. Two different linearization architectures, Predistortion (PD) and Feedforward are studied. A simple circuit of variable gain predistorter (APD) was implemented with tsmc SiGe BiCMOS technology. The APD amplifier provides a 7.8dB gain with input better than 10dB, output return loss is 7dB and has output P1dB of 17.9dBm, output IP3 of 30dBm at Vbep=0.9V, the maximum PAE of 37%. A simple differential amplifier using feedforward technique was implemented on a single chip by tsmc SiGe BiCMOS technology. The bias point and device size ratio of differential amplifier should be carefully chosen to get proper third order nonlinearity for the IM3 cancellation. The feedforward amplifier provides a 7.06dB gain with input better than 16dB, output return loss is 8.5dB and has output P1dB of 14.4dBm, and output IP3 of 31dBm, the maximum PAE of 24.5 %. Chapter five reports a high average efficiency power amplifier for W-CDMA and WLAN applications. Doherty amplifier and DC-DC converter amplifiers are investigated. The Doherty amplifier was implemented with tsmc CMOS technology, which is provided a 6.5dB gain with input better than 16dB, output return loss is 3dB and has output P1dB of 20dBm, output IP3 of 31dBm, the PAE of 24.5 %. The DC-DC converter amplifier was implemented by tsmc SiGe BiCMOS technology, which is provided a 9.5dB gain with input better than 18dB, output return loss is 5dB and has output P1dB of 16.8dBm, output IP3 of 30dBm, the maximum PAE of 42 %.
顯示於類別:	[電機工程研究所] 博碩士論文

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