為了高度整合不同功能的模組，系統單晶片技術日趨重要。但傳遞模組間訊息的晶片內部拉線，卻因延遲過長，面積過大以及高複雜度而限制了晶片的效能，尤其以全域性晶片內部拉線更為嚴重。 因此，在此論文中，我們首先根據不同製程下的晶片內部拉線，分析其特性和趨勢，以期在配合電路設計之需要下，能建立較精準的拉線模型。另外，我們也提出應用在晶片內部的序列化傳輸架構，配合所分析的拉線模型，我們設計出一序列化收發器及比較用的一平行化收發器。採用序列化架構的好處是可減少拉線面積及複雜度但不犧牲電路的操作速度。 我們採用台積電130微米 1P8M CMOS 製程，收發器的操作速度分別是5 Gbps 和 4 Gbps，而功率消耗在每條路徑下為0.8 mW 和 2.7 mW，而在同樣的操作速度下，序列化架構拉線面積只有平行化架構拉線面積的一半。 Due to the ability of integration many modules with different functions, the system-on-chip is becoming a very interesting solution system method. However, on-chip interconnects that transmit signals between inter-modules limit the performance of chip due to long wire delay, large area, large power consumption and high interconnect complexity. It is especially serious in global on-chip interconnect. Therefore, in this thesis, we firstly analyze characteristics and trends of the on-chip interconnect with scaling technology nodes. In terms of these analyses, we can establish more accurate interconnect models and it is useful in designing circuits for interconnetcs. Besides, we use serial link technique in on-chip application. With the interconnects models, we design a serial transceiver and a parallel transceiver for comparison. The advantages of serial transceiver are to reduce the interconnect area, reduce interconnect complexity without sacrificing the operational speed of system. We adopt tsmc 0.13 um 1P8M CMOS process to implement our design, and the operational speed are 5 Gbps and 4 Gbps respectively. The power consumption per channel are 0.8 mW and 2.7 mW respectively, and the interconnect area of serial transceiver is half of parallel one at same operational speed.
