具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計; Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/9881

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/9881

題名:	具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計;Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques
作者:	賴敬文;Ching-Wen Lai
貢獻者:	電機工程研究所
關鍵詞:	鎖相迴路;寬範圍操作;wide range;adaptive bandwidth;pll
日期:	2005-07-08
上傳時間:	2009-09-22 11:58:44 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	隨著超大型積體電路設計在速度的效能上快速的增加，而現在的單位面積中所包含的電晶體越來越多，所導致的延遲相對提昇，在晶片組設計中精確的時序脈波是必須的，尤其目前朝向單晶片系統設計(System-On-a-Chip Design)，在不同的子電路方塊當中常常會發生工作相位不同，或時脈偏斜(clock skew)所造成時脈不同步現象而嚴重威脅系統運作的正確性，而有誤動作的情況發生，因此，在主時脈進入子電路方塊之前通常會利用鎖相迴路(PLL)作相位校準的動作，使得所有晶片內各子電路的工作時脈同相位。而鎖相迴路在設計上最大的挑戰，除了像低抖動(low jitter)、快速鎖定、低功率消耗等效能上的改善外，固定的電路參數限制使得一般的鎖相迴路僅能使用在特定規格上系統，降低了其應用性。而頻寬(Wn)、相位邊限(phase margin)和阻尼因素(damping factor)等等系統參數，決定了鎖相迴路整個系統的抖動(jitter)和穩定度(stability)。本論文針對鎖相迴路電路上的限制，利用數學公式的推導，找出迴路參數間的關係，再利用Time to Digital Converter (TDC)、programmable current mirror等外加電路，設計出具有寬範圍操作的鎖相迴路。頻寬可隨不同的狀態去調整，使抖動的影響降到最低；而相位邊限和阻尼因素的固定可確保鎖相迴路的穩定性。本篇論文以TSMC 0.18μm 1P6M CMOS 製程來實現，工作電壓為1.8V。鎖相迴路的輸入參考頻率為5MHz-100MHz，輸出的操作頻率為100MHz-1GHz，週期抖動(period jitter)均小於輸出頻率的1.8%，而在操作頻率為1GHz、除頻器除數為200的狀態下，功率消耗為26.86mW。 When the efficiency of the speed with the very large-scale integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, especially the SOC (System-On-a-Chip Design ) is developed, however, there is often phase error or clock skew which generates asynchronous phenomenon in different sub-circuit blocks, and it always causes mistakes to affect accuracy of the system. In this reason, the phase locked loop (PLL) is used to correct the clock phase when the major clock inputs the sub-circuit, and it can lead the operation clock of the sub-circuit into the same clock phase. The challenge in designing the PLL, besides the improvement of the performance like low jitter, fast locking, and low power consumption, the restrictions of fixed loop parameters make the normal PLL just used in the specific standards, and that reduces the applications of the PLL. The loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this thesis employs formula derives to find the relationship between the loop parameters. Furthermore, we use time to digital converter (TDC), programmable current mirror (PCM) to design a PLL that has wide range applications. In the proposed circuit, the loop bandwidth can adjust in different states, and the fixed phase margin and damping factor can keep the stability of the PLL. We use the TSMC 0.18μm 1P6M CMOS process with 1.8-volt supply voltage in this thesis. The input reference frequency is 5MHz-100MHz, the output operation frequency is 100MHz-1GHz, and the period jitter is less than 1.8% of the output frequency. The power consumption of the proposed PLL is 26.86mW at 200 multiplication factor, 1GHz operation frequency.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	大小	格式	瀏覽次數

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....