本論文以矽半導體製程，所製作之高頻金氧半電晶體為主軸，藉由與矽晶圓廠之計畫合作案，來了解次微米元件特性，並學習設計射頻電路。 首先於第二章裡，針對0.13μm製程之P型金氧半電晶體，利用高頻量測系統測試元件，並藉由所量得之資料，加以探討元件於50 MHz~20.05 GHz之高頻特色，並試著建立其高頻元件模型，並針對元件之高頻與功率特性，討論其最佳之佈局。 在第三章中，相同藉由量測0.13μm P型金氧半電晶體元件，於高頻與低頻下之雜訊表現，並比較N型與P型金氧半電晶體之低頻雜訊。相同地，亦針對元件之雜訊特性，討論其最佳之佈局。 第四章裡，利用0.18μm之1P6M製程，試著設計915 MHz之被動式射頻辨識系統。 With the technology of Si-base device scaling down, CMOS had the better high frequency performance to design the consumption wireless products. Thus, this thesis is a study with the sub-micron CMOS technology. It had understood the high frequency characteristic by cooperating with the project of the silicon foundry, and learned the radio frequency circuit design. In chapter 2 and 3, it will be to discuss the high frequency, power performance and noise characteristic of 0.13μm CMOS high frequency devices. Then, t the optimum layout structure for theses performances will be considered and defined. A passive UHF RFID system was described in chapter 4. Some frond-end circuits of the reader terminal will be tried to realize by using 0.18μm 1P6M CMOS process.
