本論文的主要目的是藉由製程的探討進而改善大面積矽偵測器的漏電流及崩潰電壓。在製程方面針對墊氧化層的沈積方式、不同的前段製程、金屬層材料、以及晶背蝕刻技術等技巧做比較及研究，目的均是在減少及抑制缺陷的產生，進而使元件特性獲得改善。 此外，在元件結構方面還利用實驗測試鍵（test-key）及模擬軟體的協助，來獲得更佳的元件幾何參數，例如防護圈配置及正面電極延伸長度等。 In order to obtain the better performances, such as lower leakage current and higher breakdown voltage, of a large-area silicon strip detector. Its device the structure design and process improvements have been studied in this thesis. Several different processes had been used to fabricate the detectors and the obtained device characteristics were compared. A suitable process of pad oxide could reduce the Si/SiO2 interface defects, and the improved front-end and metallization processes could also reduce detector leakage current. The one with the multiple guard-rings with reduced spacing could be used to obtain a better device performance than the one with uniform spacing and the suitable metal overhang could reduce the device leakage current, as evidenced by the verification of simulation data with experimental results of test-keys. Also, it had been concluded that the sidewall junction of P+-strip was the main source of device leakage current.
