隨著半導體技術的發展，設計電路的驗證（verification）工作也相對變得困難。並且，對於現今複雜的大電路而言，為了達到完整的驗證涵蓋率，所以龐大的測試向量（test pattern）將是必須的。而最為普遍的邏輯模擬器（logic simulator）雖然擁有高度的控制性與完全的觀察度（observability）。不過，將會造成冗長的模擬時間。因此，在模擬速度與驗證成本的考量下，往往會採用現場可程式化閘陣列（Field Programmable Gate Array，FPGA）來快速雛型化設計電路，並完成電路驗證工作。然而，在FPGA的硬體模擬過程中，對於內部電路的觀察度則是相當的低，造成驗證工作的不便。 因此，我們的學長提出了一個“取樣方法”[3]，紀錄FPGA的內部行為並且在軟體上完整的呈現出我們所感興趣的那段波形。這樣一個擁有完全觀察度的方法，除了對整體電路只需做一次完整的編譯合成動作外，也解決了有限取樣深度的問題。然而，這個方法在某些架構的電路上，並不是很實用。尤其針對設計電路中的記憶體部分，只允許特殊的記憶體合成電路架構才可使用此“取樣方法”。並且，複製一份與待測記憶體一樣大小的儲存空間當成取樣架構的一部份，對FPGA而言，太耗費硬體資源。 在本篇論文中，我們將針對“取樣方法”更進一步地改善，使之更適用於現今複雜的設計電路中。最後，我們由實驗結果證實改進後的效率。 With the development of semiconductor technology, the verification process becomes quite difficult. Especially for modern complex designs, we often require a huge number of input patterns to verify the complex system behaviors. In this situation, although software simulation can provide full controllability and observability during the verification process, the simulation speed is too slow. Therefore, hardware emulation such as FPGA is more popular to gain high simulation speed. However, it is very hard to debug due to the poor visibility of internal nodes. In order to solve this problem, “Snapshot Method” was proposed in [3]. It “records” the internal behaviors of FPGA and “replays” those behaviors in our interesting period in software simulator. In this kind of approaches, we can have full observability with high simulation speed during the verification process. However, the limitation of this approach is the limited resources on FPGA especially for the large designs which have include a lot of memory device. Therefore, we propose a method to reduce the hardware overhead for the snapshot approach in this thesis. The experimental results have shown the efficiency of using our approach.
