適用於地面/手持式數位視訊廣播的雙模式外部接收機之超大型積體電路設計; VLSI Design of the DVB-T/DVB-H Dual Mode Outer Receiver

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Title:	適用於地面/手持式數位視訊廣播的雙模式外部接收機之超大型積體電路設計;VLSI Design of the DVB-T/DVB-H Dual Mode Outer Receiver
Authors:	林建安;Chien-An Lin
Contributors:	電機工程研究所
Keywords:	地面/手持式數位視訊廣播;李德所羅門解碼器;維特比解碼器;DVB-T;Viterbi Decoder;Reed Solomon Decoder;DVB-H
Date:	2006-07-06
Issue Date:	2009-09-22 12:02:17 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	電視自從問世以來經歷過了兩次重大的革命，一次是在一九五四年的從黑白電視演進到彩色電視，另一次是從類比電視演進到數位電視(DTV)，臺灣在二零零六年開始開播。臺灣採用了歐洲電信標準聯盟(ETSI)的標準:地面數位視訊廣播(DVB-T)來當作我們數位電視的標準，一個DVB-T的基頻接收機包含內部接收機和外部接收機，我們主要致力於雙模式的外部接收機，能同時支援地面和手持式兩種標準。一顆根據ETSI EN 300 744 - V1.5.1標準，適用於地面/手持式數位視訊廣播的雙模式外部接收機被提出在本論文中。外部接收機包括內部解交錯器、維特比解碼器、外部解交錯器和李德?所羅門解碼器。內部解交錯器和外部解交錯器是用來還原資料的排序，維特比解碼器和李德?所羅門解碼器以連接式前置錯誤更正碼的形式來降低位元錯誤率。因為DVB-T和DVB-H的有效位元率根據操作時的參數而是固定的，所以我們主要只考慮面積和功率的問題。在維特比解碼器裡，我們使用了兩級解穿刺的方法來對接收的碼字做解穿刺，能夠避免輸入端緩衝的使用。另外使用了一個64x64單端的sram來當作我們的回朔單元，能同時兼顧回朔長度和輸出率的考量。然後在李德?所羅門解碼器裡，我們提出了modified PrME cell來解我們的關鍵方程式同時能降低面積的使用。最後在內部解交錯器和外部解交錯器裡，大部分有關資料暫存的部分我們都只使用單端的sram來實現。在TSMC 0.18um 1p6m CMOS 製程中，一顆根據DVB-T和DVB-H標準以超大型積體電路設計之雙模式外部接收機被實現在核心面積為1.58 x 1.58 平方公釐的原型晶片內，以驗證所提出雙模式外部接收機的架構。其操作頻率達到40 MHz時，在DVB-T標準下且傳輸模式為8K mode、碼率為7/8 和調變方式為64 QAM時，提出的外部接收機可以得到31.67 Mb/s 解碼率，這是在DVB-T標準中所要求最高的解碼率。 The television presented to the public experiences two important revolutions. One is from black and white television to color television in 1954. The other is from analog television to digital television (DTV) in 2006 of Taiwan. Taiwan adopts European Telecommunications Standards Institute (ETSI) standard: Digital Video Broadcast – Terrestrial (DVB-T) as our DTV specification. A DVB-T baseband receiver comprises inner receiver and outer receiver. Our works focus on the dual mode outer receiver. It supports not only the DVB-T but also DVB-H (handheld). A DVB-T/DVB-H dual mode outer receiver based on ETSI standards: EN 300 744 - V1.5.1 and TR 102 377 – V1.2.1 is proposed in this thesis. The outer receiver includes inner deinterleaver, Viterbi decoder, outer deinterleaver and Reed Solomon decoder. Inner deinterleaver and outer deinterleaver are used for data restore. Viterbi decoder and Reed Solomon decoder are used as concatenated forward error correction code for better BER. Because the useful bit rate of DVB-T and DVB-H is fixed according to the operating parameters and the highest data rate is not the bottleneck of each module of outer receiver. So our works only concern the area and power. In Viterbi decoder, we use a two-stage depuncture scheme to depuncture the received codeword, it benefits the disuse of input buffer. And use a size of 64x64 single port sram as the trace back unit, it gives consideration to trace back length and throughput rate. Then, we propose the modified PrME cell for the key equation solver to lower the area in Reed Solomon decoder. And mostly the data buffers in inner deinterleaver and outer deinterleaver are implemented by single port sram only. A prototyping chip is implemented to verify the proposed architecture in 1.58 x 1.58 mm2 core area, and the maximum frequency can operate at 40MHz in TSMC 0.18um 1p6m CMOS process. The proposed outer receiver can obtain the highest decoding rate 31.67Mb/s when operating at 40MHz with 8K transmission mode, 7/8 code rate and 64QAM demapper for DVB-T standard.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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