適用於億元位元率混合光纖與銅線之電信乙太接取網路技術系統之盲目等化器和時序同步電路設計; Blind Equalizer and Timing Recovery Circuit Design for 100Mbps Receiver of Mixed Copper/Fiber EFM Systems

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9987

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9987

Title:	適用於億元位元率混合光纖與銅線之電信乙太接取網路技術系統之盲目等化器和時序同步電路設計;Blind Equalizer and Timing Recovery Circuit Design for 100Mbps Receiver of Mixed Copper/Fiber EFM Systems
Authors:	蔡明雄;Ming-Shiung Tasi
Contributors:	電機工程研究所
Keywords:	盲目等化器;時序同步;電信乙太網路接取技術;Timing recovery;Blind equalizer;EFM
Date:	2006-07-06
Issue Date:	2009-09-22 12:02:33 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	網際網路的應用越來越廣泛，現有傳輸系統的頻寬已經逐漸無法滿足用戶的需求。從傳統的撥接網路到目前的非對稱數位用迴路(ADSL)和纜線數據機(Cable modem)，用戶端到局端的傳輸速度一直是網路頻寬提昇的頻頸所在。因此無論是頻寬或是價格都難以讓使用者接受。假如我們將網路訊號直接傳送到用戶端，不經由其他額外的編碼，則網路頻寬至少由10Mbps起跳，而且可以節省一些不需要的傳輸設備。因此無論在價格或傳輸速度都較現有架構更具有競爭性。這就是EFM系統的最主要的優勢所在。在本篇論文中，我們建構了一個EFM系統的接收器包含了盲目等化器和時序同步電路。使用Matlab語言進行有限精準度的系統模擬。在此系統中資料傳輸率是100Mbps。而時序同步電路包含時序偵測，迴路濾波器，數值震盪器(NCO)電路。利用鎖相迴路(PLL)和NCO去控制ADC的取樣相位，而更正範圍是 200ppm。 In recent years, all kinds of network application have been develoed, and bandwidth is not satisfied with appetite of consumers. From Modem to present Asymmetric Digital Subscriber Line(ADSL) and Cable Modem, the bottleneck is user’s bandwidth develop(First Mile/Last Mile). The speed is unable to promote, and the price of the ethernet service is a very heavy burden to users. If ethernet connects directly to user, then the ethernet signal will transmit to user. Hence, this will save unnecessary transmit equipment, bandwidth and has at least 10 Mbps data rate. We build EFM receiver simulation platform utilizing Matlab with finite wordlength. This simulation includes blind equalizer, timing recovery loop. In this simulation, equalizer coefficients convergence and does not need any training sequence. This equalizer can operate at least at data rate of 100Mbps with system requirement, where a 9bit ADC is used for sampling the receiver signal. And, we utilize some techniques to reduce the circuit area .The timing recovery loop contains timing extracting circuit, loop filter and NCO. The timing error detects from equalizer output. We utilize PLL and NCO to adjust sampling phase of ADC. The correction range of timing recovery loop is ±200ppm.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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