現在的晶片設計，對於訊號同步電路越來越重視，所以在混和訊號電路裡有鎖相迴路(Phase-Locked Loop, PLL)和延遲迴路(Delay-Locked Loop, DLL)被廣範的運在晶片設計裡，但這兩種電路需要考慮幾個問題，第一點因為是閉迴路系統，所以有頻寬問題，需要設計電容來增加電路的穩定性，第二點在需要花幾十個時脈週期以上才能鎖定，在這過程中需要較大的功率消耗，有鑒於此，我們設計同步複製延遲電路。 傳統的同步複製延遲電路有兩個主要的缺點，第一點是輸入訊號責任週期受到限制，第二點是是靜態相位誤差太大，使得傳統的同步延遲電路只能廣範地運用在記憶體模組裡，為了讓同步延遲電路能運用在更廣的範圍，我們會針對這兩個缺點作改善，本篇論文後有量測結果，以證明的確可以改善這兩個缺點。 With the evolution of CMOS process technology, the clock synchronization becomes truly an important issue. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems in order to suppress the clock skew. There are two issues to solve in the two circuits. First, both PLL and DLL are the feedback systems which are bandwidth issue. These circuit needs to design capacitance in order to increase stability. Second, during the lock-in frequency acquisition process, it results in a large standby current, which causes lots of power dissipation. Therefore, we design digital synchronous mirror delay circuit. There are major two issues in conventional synchronous mirror delay circuit. First, the input signal clock is not arbitrary duty cycle. Second, the static phase error is much larger. Therefore, conventional synchronous mirror delay circuit often applied in many memory modules. In order to apply in large range, we improve the two disadvantages. The proposed SMD which measure result list final chapter can solve the two issues.
