適用於地面式數位電視廣播系統之平行架構記憶體式快速傅立葉轉換處理器設計 ;Design of Parallel Memory-Based FFT Processors for DVB-T System

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Title:	適用於地面式數位電視廣播系統之平行架構記憶體式快速傅立葉轉換處理器設計;Design of Parallel Memory-Based FFT Processors for DVB-T System
Authors:	唐瑋謙;Wei-Chien Tang
Contributors:	電機工程研究所
Keywords:	記憶體式快速傅立葉轉換;地面式數位電視廣播系統;DVB-T;Memory-based FFT
Date:	2007-01-08
Issue Date:	2009-09-22 12:02:50 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	由於通訊系統與網路的普及，使得人們對網路的依賴度越來越高。近來無線網路的發達，解決了有線網路的不便性，可以無所不在自由的上網，加深了大眾對無線網路的渴望，因此又造就更多的無線通訊系統，衍生出各式各樣的無線應用，無線通訊已成為未來不可或缺的重要技術。在現有的數位通訊系統中，正交分頻多工系統(OFDM-Orthogonal Frequency Division Multiplexing)是最常被拿來使用的調變技術，如: ADSL、DVB、802.11a 等等。OFDM與其他單載波調變系統最大的不同是它採用了多載波的調變技術，每個載波間皆為正交，大大節省了頻寬，提高單位時間的傳輸量。在硬體實現方面，透過快速傅立葉與反快速傅立葉轉換(FFT/IFFT)來達到調變與解調變。本論文中分析了幾種快速傅立葉轉換演算法的複雜度與其硬體架構設計。在傳統架構中可分為管線式(Pipelined)與記憶體式(Memory-based)架構，前者有著高產出量(Throughput)與簡易控制單元的優點，但是其面積相對較大，後者則反之。本論文中主要為設計一Radix-2 的記憶體式快速傅立葉轉換處理器。首先藉由切換存取的記憶體來簡化控制單元，再將其基本架構擴展並採用平行處理以提高產出量，同時保留記憶體式架構面積小的優勢，達到速度快、控制簡單、面積小的優點，更可依照所需應用調整其架構，實現有效率的快速傅立葉轉換器。 Due to the popularity of communication system and internet, people become more and more relying on the internet. Recently, the progress of wireless internet resolves the inconvenience of wired internet. People can log on the internet anytime and anywhere which deeply increases the aspiration for wireless internet. Therefore, the situation brings up with more wireless communication systems and develops various kinds of wireless application. Now the wireless communication has become the inevitable important technique in the future. Among the existing digital communication system, OFDM-Orthogonal Frequency Division Multiplexing is the most frequently used modulation technique. For example: ADSL, DVB, 802.11a, etc. The most different between OFDM and other single-carrier system is that it uses the modulation technique of multi-carrier. Each orthogonal carrier saves bandwidth greatly and rises up the throughput of the time per unit. In the aspect of hardware realization, it achieves modulation and demodulation through FFT and IFFT. In this thesis, we analyze several kinds of complexity and the hardware architecture designs of FFT algorithm. Under the traditional structure, it can split into pipeline and memory-based architecture. The former has the strengths of higher throughput and easier control unit but its hardware area is larger. However, the latter one is in the opposite. The thesis is mainly to design a memory-based architecture of Radix-2. First, switch location of memory to simplify control unit. Then extend the basic structure and utilize parallel processing to increase throughput. In the meantime, keep the advantage of small area of memory-based architecture to achieve the strengths of speed up, easy control and small area. It even can adjust the structure based on what you need to apply to realize FFT processor efficiently.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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