應用於次世代被動光纖網路傳輸之高速正交分頻多工傳收器設計; High Speed OFDM Transceiver Design for Next Generation PON Communication

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Title:	應用於次世代被動光纖網路傳輸之高速正交分頻多工傳收器設計;High Speed OFDM Transceiver Design for Next Generation PON Communication
Authors:	張智翔;Chih-Hsiang Chang
Contributors:	電機工程研究所
Keywords:	被動光纖網路傳輸;正交分頻多工;PON;OFDM
Date:	2009-11-14
Issue Date:	2010-06-11 16:20:24 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	光纖網路傳輸擁有高速、長距離的優勢使得發展10Gbps的次世代被動光纖網路 (Next Generation-Passive Optical Network) 為必然趨勢，在此高速傳輸下衍生出成本過高、實現困難的問題，因此將OFDM技術應用在光纖系統之研究為近年來熱門的討論主題。在本論文中，基於應用在光纖系統的OFDM架構，我們將提出可以使用任意子載波來偵測同步非理想效應之架構，以提高有限頻帶中能使用的頻寬，並且提出一個結合取樣時脈同步與等化器，因而系統不需要多做同步電路，並使此架構可適用在10 Gbps PON系統中。而在此高速應用中，所設計的電路能否達到光纖系統的高速需求與低成本最為重要，因此在硬體考量方面，本論文實現系統中的關鍵電路，高速FHT硬體，並應用於高速光纖OFDM系統中。電路設計使用90nm製程，核心面積為0.476x0.451 mm2為，核心時脈312.5MHz，在1.0V的電壓下，晶片功率為27.00mW。 The advantages of optical fiber communications are high speed and long distance as a result of low transmission loss. To develop the Next Generation Passive Optical Network (NG-PON) is one of the main focuses. Particularly, the key issue is the cost-efficient device been feasible. Thus, OFDM technique in optical communication to increase spectral efficiency becomes popular in this domain. In the thesis, we propose a new architecture for 10Gbps PON to detect the sampling clock offset using any subcarrier in each OFDM symbol. The proposed architecture joins timing recovery synchronization and equalization to reduce the cost of conventional timing synchronization for cost-efficiency and achieve a superior performance. In hardware implementation, we propose the high speed FHT hardware to achieve high-speed circuit requirement in optical fiber communications. Whole circuit, designed in 90 nm CMOS process, occupied 0.476x0.451 mm2 of core area, and totally consumes 27.00 mW in 1.0 Volt supply voltage at the clock rate of 312.5 MHz.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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