考慮電源完整性與輸出/入埠限制之積體電路設計配置方法; VLSI Design Planning with Power Integrity and I/O Constraints

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/25822

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/25822

Title:	考慮電源完整性與輸出/入埠限制之積體電路設計配置方法;VLSI Design Planning with Power Integrity and I/O Constraints
Authors:	呂昭宏;Chao-Hung Lu
Contributors:	電機工程研究所
Keywords:	輸出/入埠配置;電源完整性;I/O Planning;Power Integrity
Date:	2010-01-26
Issue Date:	2010-06-11 16:21:00 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	超大型積體電路設計日益複雜，加上奈米效應使得晶片與封裝的設計變得更加困難，因此電子設計自動化產品也必需不斷的進步以符合時代的需求。由於市場需求，電路需擁有較高的效能與較低的供應電壓等特性，且因所需的輸入/輸出埠不斷增加造成封裝設計上困難度不斷的增加。在此論文中，我們提出了幾個新的佈局規劃與配置方法。這些方法不只可以解決電源雜訊上的問題，還可以考慮封裝設計以及堆疊晶片的設計問題。關於電源雜訊中的同時性邏輯轉換雜訊問題方面，我們採用了一個二階式技術:佈局規劃與電容插入。首先利用佈局規劃的方法盡可能抑制雜訊，之後再藉由去耦合電容插入的方法，來改善雜訊問題。因佈局規劃與電容插入的方法均有考慮到整體面積的問題，因此最後因為改善雜訊而付出的面積代價是非常小的。關於電源雜訊中的電壓降雜訊與封裝設計方面，我們採用了一個推算輸入/輸出埠排序的方法來解決此一問題，主要是因為輸入/輸出埠的排序會影響到晶片核心的電壓降雜訊與封裝繞線複雜度。雖然現今的輸入/輸出埠數量非常的大，但我們的推算方法只需要花費O(n)的時間就可推算出最適的位置。另外，堆疊設計是最能有效提供高效能晶片的設計方法，在論文中我們提出了一個分割方法來有效配置輸入/輸出埠的位置，且此一方法能同時考量連接元件數量。最後再用佈局規劃方法來改善對於最後整體晶片面積的影響。 In modern VLSI deigns, manufacturing issues have complicated the designs of chips as well as packages. Moreover, due to the requirement of the market, modern circuits have higher functionality, lower supply voltage and more I/Os. These conditions increase complexity of chip designs. In this dissertation, we present some I/O plan and floorplan methods to solve these problems. They cannot only be applied to mitigate the power supply noise in the core, but also can consider the package designs, and stacking IC designs. For the simultaneous switching noise, our method adopts a two-stage technique of the floorplan followed by the decoupling capacitance (decap) insertion. In the floorplan, the area and noise are evaluated to find a noise-driven floorplanning result. Then, we use a noise-driven decap planning approach to inserting minimal decaps into a floorplan. For IR-drop and the packages issues, we adopt a finger/pad assignment method to solve these problems. Our finger/pad assignment is a two-step method: we first solve the package design problem, then try to minimize IR-drop by switching finger/pad locations. In addition, since stacking IC is promising to the development of a high-performance IC, in this dissertation, we propose a partition approach to minimizing the 3D-vias and balancing the I/O number for each tier in stacking IC. Finally, we perform a floorplanning to show the importance of the aspect-ratio factor in stacking IC.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	1056	View/Open

社群 sharing

Loading...