0.5-6 GHz low-voltage low-power mixer using a modified cascode topology in 0.18 mu m CMOS technology

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题名:	0.5-6 GHz low-voltage low-power mixer using a modified cascode topology in 0.18 mu m CMOS technology
作者:	Liang,KH;Chang,HY
贡献者:	電機工程學系
关键词:	ANALOG MULTIPLIER;0.18-MU-M CMOS;RF CMOS;PERFORMANCE;DC
日期:	2011
上传时间:	2012-03-28 10:13:11 (UTC+8)
出版者:	國立中央大學
摘要:	A broadband low-voltage low-power down-conversion mixer using a 0.18 mu m standard CMOS process is presented. The proposed mixer uses a modified cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency (RF) of 2.4 GHz, a single-sideband (SSB) noise figure of 15.2 dB, and an input third-order intercept point (IIP3) of 0 dBm. Moreover, the chip area of the mixer core is only 0.15 x 0.23 mm(2). The measured 3 dB RF bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (V(DD)) can be scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be compatible with an advanced 90 or 65 nm CMOS technology.
關聯:	IET MICROWAVES ANTENNAS & PROPAGATION
显示于类别:	[電機工程學系] 期刊論文

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