A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

NCU Institutional Repository > 資訊電機學院 > 電機工程學系 > 期刊論文 > Item 987654321/52019

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/52019

題名:	A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit
作者:	Cheng,KH;Hong,KW;Chen,CH;Liu,JC
貢獻者:	電機工程學系
關鍵詞:	SYNCHRONOUS MIRROR DELAY
日期:	2011
上傳時間:	2012-03-28 10:13:26 (UTC+8)
出版者:	國立中央大學
摘要:	This study proposes a high precision fast locking arbitrary duty cycle clock synchronization (HPCS) circuit. This HPCS is capable of synchronizing the external clock and the internal clock in three clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control circuit, the HPCS operates correctly with an arbitrary duty cycle (25%-75%) clock signal. Second, the HPCS works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Finally, the HPCS can enhance the resolution between the external clock and internal clock with a fine tuning structure. After phase locking, the maximum static phase error is less than 20 ps. The proposed chip is fabricated in a TSMC 130-nm CMOS process, and has an operating frequency range from 300 to 600 MHz. At 600 MHz, the power consumption and rms jitter are 2.4 mW and 3.06 ps, respectively. The active area of this chip is 0.3 x 0.13 mm(2).
關聯:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
顯示於類別:	[電機工程學系] 期刊論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	823	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing