應用於生醫訊號之低功率數位降頻濾波器;Low Power Decimation Filter for Biomedical Signal

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/53183

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/53183

Title:	應用於生醫訊號之低功率數位降頻濾波器;Low Power Decimation Filter for Biomedical Signal
Authors:	林弘益;Hung-Yi Lin
Contributors:	電機工程研究所碩士在職專班
Keywords:	降頻濾波器;低功率;類比數位轉換器;low power;ADC;Decimation Filter
Date:	2012-01-18
Issue Date:	2012-06-15 20:23:45 (UTC+8)
Abstract:	在可攜式、可植入的生醫訊號系統之中，低功耗與低電壓設計特性在生醫晶片的應用將更趨重要。因此低功耗與低電壓的設計必需能有效的縮小晶片和電池的體積與重量，才能符合可攜式的生醫儀器之輕薄短小與維持電池長效性的要求。在生醫系統中，高解析度且低功耗的類比數位轉換器(ADC)是核心電路之ㄧ。由於三角積分調變器(SDM)之類比數位轉換利用超取樣技術可降低前端類比濾波器設計的複雜度，因而在低頻訊號處理之應用廣泛。然而SDM類比數位轉換器，需要搭配後級數位降頻濾波器，濾除高頻雜訊，並降低取樣頻率。因此，本論文的研究目標為實現應用於三角積分調變器之類比數位轉換器中，低功耗、小面積的數位降頻濾波器。本論文之低功耗的數位濾波器設計，採用Polyphase decompositions、CSD(Canonical Signed Digit)與CSE (Common Subexpression Sharing)設計方法。並提出最小濾波器設計面積搜尋法，找出最小面積且效能符合的濾波器係數。此外，實際採用FPGA實現所設計之數位降頻濾波器，其信號雜訊失真比(SNDR)可達73dB，解析度可達12bit。最後，使用TSMC 013G完成晶片設計流程驗證低功率消耗設計方法，其功率消耗305uW，晶片面積為0.40mm2。In portable and implementable biomedical systems, there are two more important design issues in the biomedical chip than other applications, which are very low power consumption and low power supply voltage. Besides, the low power design has to effectively shrink down the chip area and battery volume to satisfy portable and long battery lifetime requirements of biomedical instruments. The high resolution and low power analog-to-digital converter (ADC) is a key component in biomedical systems. By taking the advantage of oversampling technique, the sigma-delta (SD) modulation can relax the design complexity of the analog front end anti-aliasing filter. However, the SD ADC needs the digital decimation filter at the SD modulator output to remove the high frequency noise and down-sampling data. This study proposes a low power and minimized circuit area digital decimation filter design in the SD ADC. Poly-phase decomposition, canonical signed digit (CSD) and common sub-expression sharing (CSE) approaches are applied in the design to achieve low power target. Furthermore, the “search method to minimize filter area” is also proposed to find out the filter coefficients with minimized circuit area and suitable performance. The proposed design is first realized on Altera FPGA emulation board. The performance can achieve 73dB signal-to-noise and distortion ratio (SNDR) and 12bits resolution. Our design is also accomplished in TSMC 0.13um CMOS process with 305uW power consumption and 0.40mm2 chip area to demonstrate the proposed digital decimation filter design in the SD ADC.
Appears in Collections:	[Executive Master of Electrical Engineering] Electronic Thesis & Dissertation

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