泛用型電路介面行為模型產生器及其圖形化使用者介面; A Generic Behavior Model Generator for Interface Circuits with Graphical User Interface

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題名:	泛用型電路介面行為模型產生器及其圖形化使用者介面;A Generic Behavior Model Generator for Interface Circuits with Graphical User Interface
作者:	林筠菁;Lin,Yun-Jing
貢獻者:	電機工程學系
關鍵詞:	行為模型;產生器
日期:	2013-07-30
上傳時間:	2013-08-22 12:12:50 (UTC+8)
出版者:	國立中央大學
摘要:	隨著製程演進以及電路應用層面日趨廣泛，積體電路的設計複雜度日漸增高，所需的電路模擬驗證時間也大幅增加，連帶拖慢了整個設計流程完成的時間，尤其是在類比及數位電路之整合模擬(co-simulation)方面，仍舊有許多難以克服的因素，使得混合訊號設計的整合模擬目前仍有一定的困難度。以行為模型(behavior model)取代原始類比電路設計區塊，將模擬的層級提高，也是一個縮短模擬時間的方法。準確地建立行為模型後，能夠將行為模型與數位電路區塊整合模擬，檢驗類比與數位電路設計區塊之間訊號傳輸，以及電路反應行為是否正確並且符合預期。現今已存在的行為模型產生器(behavioral model generator)，大多是針對特定的電路，例如：專用於類比數位轉換器電路(analog to digital converter, ADC)抑或是鎖相迴路電路(Phase-locked loops, PLL)電路，難以廣泛運用於各種不同的系統中。本論文對行為模型建立做研究，旨在以整合已存在之電路模型區塊的方法，提升行為模型產生器的泛用程度，依據電路模型區塊資訊以及區塊間訊號傳遞關係，整合各電路區塊自動產生相對應之電路介面行為模型(circuit interface behavioral model)，產出之行為模型可供後續應用於電路驗證程序；另外也提供圖形化介面協助使用者以更簡易的方式，指定訊號傳遞關係產生電路介面行為模型。 With the development of the semiconductor technology, more and more applications of the integrated circuits are enabled with increasing complexity. Because many devices and building blocks are included in one integrated circuit, the simulation time of the design is significantly increased, which is the main difficulty that slows down the design procedure. For mixed-signal designs, there are still many difficulties to be solved for fast co-simulation. Replacing the original analog circuit block by corresponding behavior model is a solution for speeding up the simulation. If the behavior model is built accurately, the simulation level could be raised from transistor level to behavior level that enables the co-simulation with the digital part to check the signal interactions between analog and digital parts and the expected behavior of the entire system. Previous behavior model generators are often dedicated on particular circuit structures, such as ADC and PLL. It is not easy to extend those behavior model generators for different systems. In this thesis, the target is to develop a generic behavior model generator that can integrate the existed behavior models in all design hierarchies. According to the user-provided information of the circuit blocks and the connections between then, the generator will automatically generate the hierarchical behavior model of this system incorporating the interface between circuit blocks. The generated behavior models can be applied to the following verification process. In addition, an easy-to-use graphical user interface is also provided in this work to help users specify the signal relationship of the interface model.
顯示於類別:	[電機工程研究所] 博碩士論文

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