應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製; Implementation on Fully Integrated Wideband CMOS Power Amplifiers Using Transmission-Line Transformer for X/K–Ka/V-band Applications

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題名:	應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製;Implementation on Fully Integrated Wideband CMOS Power Amplifiers Using Transmission-Line Transformer for X/K–Ka/V-band Applications
作者:	郭晉瑋;Kuo,Chin-Wei
貢獻者:	電機工程學系
關鍵詞:	功率放大器;傳輸線型變壓器;達靈頓架構;磁耦合變壓器;發射機;毫米波電路;power amplifier;transmission-line transformer;Darlington topology;transformer;transmitter;millimeter-wave circuit
日期:	2013-08-13
上傳時間:	2013-10-08 15:23:52 (UTC+8)
出版者:	國立中央大學
摘要:	本論文利用tsmcTM提供的0.18-μm CMOS 與90-nm CMOS製程，實現操作於毫米波頻段之寬頻功率放大器以及K頻段小型發射機。內文在設計上分成兩部份，第一部份為應用傳輸線型變壓器於全積體整合寬頻CMOS功率放大器之研究，為解決CMOS製程在設計寬頻功率放大器時所遇到之瓶頸，如基板損耗過大、轉導能力不佳與電晶體崩潰電壓過低等問題，分別在X頻段、K至Ka頻段與V頻段設計三個功率放大器，利用傳輸線型變壓器的低損耗及寬頻特性，改善放大器操作於毫米波頻段時之性能。此外，因應不同的頻段需求，第一顆晶片搭配線性化與功率結合技術改善放大器的線性度與提升輸出功率；第二顆晶片則結合達靈頓對與疊接架構，同時提升fT與電晶體轉導能力，使得用低階製程也能在毫米波頻段下獲得足夠的增益；第三顆晶片則是採用改良過之達靈頓架構，利用電流再利用技術使消耗電流減少，同時提升放大器之增益平坦度。第二部分則是利用0.18-μm CMOS製程設計一個可應用於K頻段調頻連續波技術的小型發射機，完成整個發射機系統的設計驗證。各電路量測之特性如下： X頻段寬頻功率放大器，在未開啟預失真電路時，增益量測結果為24.4 dB，飽和輸出功率為21 dBm，1-dB增益壓縮點之輸出功率為18.6 dBm，功率增進效率（PAE）為9.9%，3-dB頻寬為6.4 GHz（6.5 GHz至12.9 GHz）；開啟預失真電路之後，其增益量測結果為 23.2 dB，飽和輸出功率提升至22 dBm，1-dB增益壓縮點輸出功率提升至20.8 dBm，功率增進效率為20.1%，3-dB頻寬為5.8 GHz（6.6 GHz至12.4 GHz）。此功率放大器在整個X頻段的範圍（8 GHz至12.4 GHz）之內，飽和輸出功率與功率增進效率分別大於21.3 dBm以及16.2%，晶片面積包含測試墊片為1.05 mm2。 K至Ka頻段達靈頓寬頻功率放大器，小訊號增益在17.8 GHz至34.6 GHz的頻段範圍內，量測結果為15.2 1 dB，同時具備不錯的增益平坦度。在26 GHz所量測之飽和輸出功率為19.5 dBm，1-dB增益壓縮點輸出功率為16 dBm，功率增進效率為10.2%，功率3-dB頻寬為15 GHz（18 GHz至33 GHz），對應的功率比例頻寬為58.8%，晶片面積包含測試墊片為0.86 mm2。 V頻段電流再利用達靈頓寬頻功率放大器，利用改良式的達靈頓架構與傳輸線型變壓器達到超寬頻的特性。其小訊號增益為16.4 dB，3-dB頻寬為26 GHz（33.3 GHz至59.3 GHz），對應的增益比例頻寬為56.2%，同時在40 GHz至55 GHz的頻段內具備不錯的增益平坦度。於35 GHz至60 GHz的頻段內，飽和輸出功率為9.9 ± 0.6 dBm，1-dB增益壓縮點輸出功率為4.7 ± 0.6 dBm，功率增進效率最高值為4.8%，晶片面積包含測試墊片為0.82 mm2。應用於K頻段之小型發射機，電路經由12 GHz壓控振盪器產生訊號之後，由倍頻器將頻率提升至K頻段，最後經由小型功率放大器把訊號推送出去。其頻率可調範圍為22.8 GHz至24.5 GHz，可調頻寬為1700 MHz，同時在此範圍內之輸出功率達14.4 0.8 dBm，對應的功率增進效率為9%至14%之間。在控制電壓為1 V，偏移中心頻率1 MHz時之相位雜訊為-99.1 dBc/Hz，整體晶片面積包含測試墊片為0.76 mm2。 A CMOS power amplifier (PA) with wideband, high output power and high efficiency is the most challenging circuit due to low-Q passive component, lossy substrate, low breakdown voltage and low maximum available gain (MAG) of the transistors, especially in millimeter-wave frequency. Therefore, broadband and low-loss impedance transformers are attractive especially in CMOS PAs. The contents of this thesis are divided into five parts. Chapter 1 gives the motivation of system applications. Chapter 2 introduces the basic theory and some design parameters of power amplifier. Chapter 3 presents several fully-integrated wideband PAs were fabricated in tsmcTM 0.18-μm and 90-nm CMOS technologies. The focus of this chapter is the research of transmission-line transformers (TLTs). TLTs can be exploited to perform broadband and low-loss impedance transformation. Therefore, three wideband PAs were designed by utilizing broadband and low-loss Guanella-type TLT as the matching networks with different frequency bands. A full X-band PA with an integrated Guanella-type transformer and a pre-distortion linearizer in 0.18-?m CMOS was implemented in the first design. The broadband performance was achieved by using transformers including a differential Guanella-type TLT (DTLT) and two magnetically coupled transformers. The linearity of PA is enhanced by feedback topology and the use of pre-distortion linearizer. Over full X-band from 8 GHz to 12 GHz, the saturated output power (Psat) and the maximum power added efficiency (PAEmax) are higher than 21.3 dBm and 16.19%, respectively. The performances of output 1-dB gain compression point (OP1dB) and PAEP1dB are significantly improved by an output power of 2.2 dBm and a PAE of 12.1%, which contributes to power back-off operation for the application of linear modulation. The chip area, including pads, is 1.05 mm2. In the second design, an 18 to 33 GHz fully-integrated Darlington PA with DTLTs demonstrated the wideband and high power performance compared with other Ka-band CMOS PAs. The Darlington cell with cascode topology was adopted as the power cell to elevate the MAG of the transistors in standard 0.18-μm CMOS technology for being capable of operating at Ka band. Moreover, utilizing broadband and low-loss DTLTs as the matching networks, the proposed PA exhibits a flat gain of 15.2±1 dB from 17.8 to 34.6 GHz. The 3-dB power bandwidth is from 18 to 33 GHz with the saturated output power of 19.5 dBm. The OP1dB of 16 dBm and PAE of 10.2% are achieved at 26 GHz under a power consumption of 711 mW. The chip size is 0.86 mm2 including test pads. In the third disign, a wideband Darlington power amplifier using DTLTs and current-reused technique was fabricated in 90-nm CMOS technology for V-Band applications. Compare to the original Darlington topology, the proposed current-reused Darlington topology achieve the same gain-extension ability while consumes less current than that of conventional one. This wideband PA exhibits a peak gain of 16.4 dB, and 3-dB bandwidths from 33.3 to 59.3 GHz. The measured result shows the saturated power of 9.9 ± 0.6 dBm from 35 to 60 GHz. The OP1dB of 5.3 dBm and PAE of 4.8% are achieved at 50 GHz. Chpater 4 develops a compact-size transmitter front-end for 24-GHz Frequency- Modulated Continuous-Wave (FMCW) applications, which is composed of voltage-controlled oscillator (VCO), frequency doubler and medium power amplifier. The measured oscillation central frequency is 23.7 GHz with the tunable frequency range from 22.8 to 24.5 GHz. The phase noise is -99.1 dBc/Hz at 1-MHz offset, and the maximum output power is 15.3 dBm. The total power consumption is 225 mW. Finally, the conclusion and future work are given in Chapter 5.
顯示於類別:	[電機工程研究所] 博碩士論文

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