以40-nm CMOS製程實現操作於100-GHz 之功率放大器設計;A 100-GHz Power Amplifier Design in 40-nm CMOS Process

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/74947

Title:	以40-nm CMOS製程實現操作於100-GHz 之功率放大器設計;A 100-GHz Power Amplifier Design in 40-nm CMOS Process
Authors:	王淳;Wang, Chun
Contributors:	電機工程學系
Keywords:	毫米波;功率放大器;發射機;Millimeter Wave;Power Amplifier;Transmitter
Date:	2017-08-11
Issue Date:	2017-10-27 16:12:43 (UTC+8)
Publisher:	國立中央大學
Abstract:	本篇論文提出一個以TSMC 40-nm CMOS製程實現操作於100-GHz之功率放大器之設計。此功率放大器電路設計為了應用於200-GHz發射機電路，避免後級電路因承受過大的功率而導致燒毀的可能性，因此設計理念不同於一般功率放大器，並未加入為了提高輸出功率的多路功率合成器的設計。論文第一部分說明功率放大器的基本設計理論，包括直流偏壓點的設計及負載線理論。第二部分則是100-GHz兩級功率放大器之設計，電路架構使用共源級組態，加入了交叉耦合電容同時提高穩定度及增益，並且使用共振耦合網路作為阻抗匹配網路及巴倫器，此功率放大器電路之模擬結果為9.49 dBm的輸出功率，功率附加效率為6.95%， 1-dB壓縮點輸出功率為7.42 dBm，頻寬為31% 第三部分則是200-GHz發射機之電路設計，此電路包含壓控振盪器、驅動放大器、功率放大器、振幅偏移調變器、二倍頻器。壓控振盪器所產生的100-GHz訊號經由驅動放大器及功率放大器放大以獲足夠的輸出功率，再經由二倍頻器將其工作頻率倍頻至200-GHz，最後經由調變器進行調變。此發射機具有-0.95 dBm的輸出功率，調變速度可達20Gb/s。 ;This thesis proposes a 100-GHz power amplifier design in TSMC 40-nm CMOS process. The power amplifier applies to the 200-GHz transmitter circuit. To avoid braking the next stage circuit, the power amplifier does not add the power combiner design which is designed for increasing the output power. The first part is the basic theories related to the design of power amplifiers, including the DC bias point of transistor and the load line theory. The second part is the design of the 100-GHz two stage power amplifiers. The common source mode is chosen in this design for its high gain characteristic. To increase the stability and gain , the cross couple capacitors is added for resonating the parasitic capacitors of the transistors. The transformers in this power amplifier are worked as the impedance matching network and balun. The power amplifier exhibits saturation output power of 9.49 dBm, maximum power-added efficiency (PAE) of 6.95%, and the output power at 1-dB gain compression point of 7.42 dBm. The 3-dB bandwidths is 31%. The third part is the design of the 200-GHz transmitter. This circuit consists of a voltage control oscillator (VCO), a driver amplifier, a power amplifier, a doubler, and an ASK modulator. The VCO generates the 100-GHz signal, and then it gets enough output power by driver amplifier and power amplifier. The operating frequency will be raised up to 200-GHz by doubler. The signal will be modulated with a digital data signal by ASK modulator in the end. This transmitter provides output power of -0.95 dBm and a data rate of 20 Gb/s at 200 GHz.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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