類比電路設計，例如類比/數位轉換器(ADC)，其性能取決於精準的電容比值。隨著半導體製程的不斷進步，電容比值的精確度受到製程變動的影響越來越嚴重。現今的電路設計工程師，多採取將單一顆大電容切割成多顆單位電容，然後並聯所有單位電容，組成陣列，來抑制製程變異造成的不匹配影響。因此，如何妥善處理單位電容陣列成為自動化佈局中很重要的課題。 現今存在數種單位電容擺放和電容佈局的方法，因此如何評斷不同的陣列和演算法的優劣成為一種很重要的議題。過去的文獻中常使用的是評估方法為總相關係數L (Overall Correlation Coefficient)，最大不匹配程度比率M (Maximum Ratio Mismatch)以及積分非線性INL(Integral Linearity)。為了使類比電路的佈局設計效果更佳，更有效率，因此需要一套更有系統的評估指標。本論文提出一種量化不匹配程度的新的評估指標，從相關係數的角度出發，利用元件的空間相關特性，考慮電路運作原理，並且採用製程能力指標的統計分析方法，來評估電容陣列的擺放的好壞。不僅能模擬兩組電容陣列，也適用於ADC電路中，多組電容陣列的連比。針對過去文獻中所出現的陣列的方法，進行分析，透過吾人的方法能找到電容陣列擺放方法中的最佳解，以供電路設計者來參考。 ;The analog circuits, such as Analog-to-Digital Converter, the yield depends on the accurate capacitance ratio. As the evolution of semiconductor technology, process variations caused the huge mismatch of the capacitance ratio. The IC designers choose to make several Unit Capacitances parallel to alleviating the process variation problem. Therefore, how to deal with those pairs of unit capacitances array became an important issue in nano-technology. There are three main methods to evaluate the performances of capacitors placements. The first is Overall Correlation Coefficient, the second is the Maximum Ratio Mismatch. The last one is the integral linearity. In order to promote the layout circuit more effectively, we proposed a new criteria to evaluate multiple capacitors array′s placements. Including the spatial correlation and statistical analysis method to determine the placements’ performances. Consider the mismatch effects, after comparing the some references, we can also find which placement could make the ADC circuit operate much more precisely.
