| 摘要: | 隨著穿戴式行動裝置的普及，越來越多的可攜帶生醫電子產品問世，除了可以針對老年及須長期照護的人口提供即時醫療監控以外，一般民眾在運動當下亦可透過裝置得知自身心跳、血壓與肌力等數據，並利用無線傳輸技術同步至行動裝置顯示並分析。由於自人體擷取出的生醫訊號一般都極其微小，如何在攜帶式裝置上不受雜訊影響下，將訊號完整的放大至可進行分析是生醫感測系統的主要訴求。因此，本電路設計即以低雜訊、低失真及低功耗為設計目標。
本論文實現一應用於生醫訊號感測之類比前端放大器，並分為低雜訊放大器(LNA)及可調式增益放大器(PGA)兩個部分，系統架構皆採用電容耦合式儀表(CCIA)架構以阻絕前端電極貼片所產生之直流偏移。在心電訊號(ECG)及腦波訊號(EEG)的應用中，需要對於1 Hz左右的訊號做擷取，若僅使用虛擬電阻作為回授來實現極低截止點將會造成低頻訊號的失真，故本設計採用積分器當作主動式回授電路來實現低頻截止點，以降低對於虛擬電阻阻值的需求，進而提高低頻訊號之線性度。積分器中的虛擬電阻則是使用壓控對稱式虛擬電阻(voltage-controlled symmetric pseudo-resistors)，以實現可調式頻寬之功能，其可調頻寬內可包含腦波訊號(EEG)、心電訊號(ECG)及眼電訊號(EOG)等生理訊號。
本電路採用台積電0.18 μm CMOS 1P6M製程，晶片面積約占0.834 mm2 (包含ESD PAD)，電源供應電壓為1.2 V，整體電路功耗為4.1 µW (包含偏壓電路) ，最大應用頻寬為4.8 kHz。透過可調式增益放大器後分別可得到54 dB、48 dB、42 dB之增益，低頻截止點為1 Hz，應用頻寬內輸入雜訊為2.28 µVrms，雜訊效率因素(NEF)為2.29。
;With the popularity of the mobile devices, more and more portable biomedical electronic products have been launched. In addition to providing immediately medical supervision for elders and people who need long-term care, these products can measure the heartbeat, blood pressure and muscle strength for people taking exercise. With the wireless transmission technology, these physiological signals detected by read-out circuit will be synchronized to mobile device for advanced analysis. Because the signals acquire from human body usually feature extreme low amplitude, the ability to completely amplify these signals in portable device without introducing noise or interference is main challenge faced by biomedical detection system. For this reason, this circuit is designed with the aim of low noise, low distortion and low power.
This thesis presents a design of analog front-end amplifier for bio-signal detection and is composed of low noise amplifier (LNA) and programmable gain amplifier (PGA). CCIA (capacitor-coupled instrumentation amplifier) architecture is applied to both parts for rejection DC offset of front-end electrode-tissue. Generally, bio-signal detection system for ECG and EEG require acquisition of low frequency signal at nearly 1 Hz. Although conventional CCIA architecture that uses pseudo-resistor as the feedback path can achieve such low cut-off pole, it will also introduce the distortion at low frequency. Instead, this thesis applies active integrator as feedback path to realize low cut-off pole. By doing so, we can reduce the demand for pseudo-resistor resistance, and then improve signal linearity at low frequency. The pseudo-resistor in the integrator applies voltage-controlled symmetric pseudo-resistor (VCSPR) to realize programmable bandwidth function. In programmable bandwidth range, this design can detect Electroencephalography (EEG), Electrocardiogram (ECG) and Electrooculography (EOG) signal.
This circuit is designed in TSMC 0.18 μm CMOS 1P6M process and the chip area is 0.834 mm2 (including ESD PAD). The power consumption is 4.1 μW for 1.2 V power supply voltage. The minimum low cut-off frequency is 1 Hz (programmable) and application bandwidth is 5 kHz. With PGA, the system gain can be 54 dB, 48 dB, 42 dB respectively. Finally, input-referred noise is 2.28µVrms and noise efficiency factor (NEF) is 2.29. |
