應用於毫米波高速通訊四相位鎖相迴路及高線性度正交調變鎖頻迴路之研製;Quadrature Frequency-Locked Loops with High Linearity I/Q Modulator and Quadrature Phase-Locked Loops for Millimeter-wave High-speed Communications

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题名:	應用於毫米波高速通訊四相位鎖相迴路及高線性度正交調變鎖頻迴路之研製;Quadrature Frequency-Locked Loops with High Linearity I/Q Modulator and Quadrature Phase-Locked Loops for Millimeter-wave High-speed Communications
作者:	胡瀚中;Hu, Han-Chung
贡献者:	電機工程學系
关键词:	振盪器;鎖相迴路;鎖頻迴路;次諧波注入鎖定;正交調變器;Oscillator;Phase-locked Loops;Frequency-locked Loops;Sub-harmonically injection-locked;I/Q modulator
日期:	2021-07-06
上传时间:	2021-12-07 13:00:04 (UTC+8)
出版者:	國立中央大學
摘要:	在現今的通訊系統中為了尋求高速資料傳輸量的需求，射頻的收發機系統的頻寬比較高優點也展現出來，其中本地振盪源當作系統中升降頻的元件有著重要的地位。而本地振盪源對於相位雜訊的規格是相當高的，當相位雜訊太差將會接連影響到接收的訊號上，會使整體系統性能降低。本論文所使用鎖相迴路可以準確提供穩定的相位頻率，而次諧波注入鎖定的技術可以有效的改善相位雜訊，再搭配無除頻器架構來使整體鎖定頻寬提升，來達到低相位雜訊、低功耗、低抖動量、高頻寬的四相位本地振盪源。第二章為X頻段多相位鎖相迴路，電路使用台積電0.18 μm互補式?屬氧化物半導體製程設計並實現，鎖相迴?包含變壓器耦合壓控振盪器、相位頻?偵測器、電荷幫浦、迴??波器、兩級電流模式除頻器及四級單相位時序除頻器。由於頻率偏移使輸出至除頻器之功率不足，導致鎖相迴路只有一半能正常運作，振盪器量測到的頻率範圍從8到8.67 GHz，鎖頻迴路量測到的頻率範圍為8.2到8.67 GHz，輸出功率為-5 dBm，距載波偏移1 MHz量測的輸出相位雜訊為-102.7 dBc/Hz，直流功耗為44.6 mW。第三章採用具有低相位雜訊低抖動優勢的鎖頻迴路架構，首先介紹次諧波注入鎖定技術，通過使用變壓器耦合的架構，可使得注入鎖定振盪器擁有更好的特性，且使用堆疊式技術設計振盪核心，提高負電阻的同時不用使用更大的功耗。根據系統模擬相位雜訊線性模型計算方法，可得知當振盪器鎖定頻寬足夠時，整體鎖頻迴路可以得到較低的輸出相位雜訊。其操作頻率從24.7到27.1 GHz，在鎖頻迴路鎖定頻率為25.5 GHz的情況下，距載波偏移1 MHz 之相位雜訊量測到為 -130 dBc/Hz，抖動量積分範圍由1 kHz 到40 MHz為15 fs，振幅誤差和相位誤差分別為0.2 dB及0.1°，電路直流功耗為55.8 mW。第四章介紹使用次諧波鎖頻迴路之2n-QAM 38-40 GHz正交調變器，使用台積電 90 nm CMOS製程來設計。由於沒有除頻器串列，因此具有較低的整體功耗、相位雜訊與抖動量，且使用次諧波注入鎖定正交鎖頻迴路與反射型調變器，該調變器具有良好線性度所造成好的調變質量與頻寬，且可以應用於各種不同調變方式的性能。由於正交鎖頻迴路的低相位雜訊和正交誤差，因此調製方案可以達到128 QAM。測得的128-QAM EVM在3％以內。在3 Gsps的符號速率下，測得的16-QAM在6％以內。整體直流功號為36.9mW。所提出的2n -QAM上調變器具有各種調變的性能，可用於毫米波高級發射機。 ;In modern communication systems, in order to meet the demand for high-speed data transmission, the advantages of the wide bandwidth of the radio frequency transceiver system have also emerged. The local oscillator source plays an important role in the system. The local oscillator source has very strict requirements for phase noise. If the phase noise is high, the signal-to-noise ratio of the transceiver degrades, as well as system performance. The phase-locked loop proposed in this paper can accurately provide stable frequency, and the injection-locking technology can effectively reduce phase noise. Moreover, a frequency-locked loop with a divider-free feedback can be adopted to widen locking range and reduce dc power consumption, phase noise, and jitter. A X-band multi-phase phase-locked loop is presented in Chapter 2. The circuit is designed and implemented using TSMC 0.18 μm CMOS process. The phase-locked loop includes a transformer-coupled voltage-controlled oscillator, a phase-frequency detector, a charge pump, a loop filter, two current-mode frequency dividers, and four true-single-phase-clock frequency dividers. Due to the frequency offset of the voltage-controlled oscillator, the power output to the frequency divider is insufficient, resulting in only half frequency range of the phase-locked loop functioning normally. The measured frequency range of the oscillator is from 8 to 8.67 GHz, and the measured frequency range of the phase-locked loop is from 8.2 to 8.67 GHz, and the output power is -5 dBm under the free-running condition. The measured output phase noise at 1 MHz offset is -102.7 dBc/Hz, and the DC power consumption is 44.6 mW. A sub-harmonically injection-locked frequency-locked loopis presented in Chapter 3, and it features low phase noise and jitter. First, the sub-harmonically injection-locked technology is introduced. By using a transformer-coupled architecture with a stacked boosting, the injection-locked oscillator can have better characteristics up to 28 GHz. The oscillation core can increase the negative resistance without using more power consumption. According to the calculated method of the system simulation phase noise linear model, it can be known that when the oscillator lock bandwidth is sufficient, the overall frequency lock loop can obtain lower output phase noise. Its operating frequency ranges from 24.7 to 27.1 GHz. When the frequency of the frequency-locked loop is 25.5 GHz, the measured phase noise at 1-MHz offset is -130 dBc/Hz, and thethe measured jitter integrated from 1 kHz to 40 MHz is 15 fs, the amplitude error and phase error are 0.2 dB and 0.1°, respectively, and the overall DC power consumption is 55.8 mW. Chapter 4 introduces a 2n-QAM 38-40 GHz IQ modulator using sub-harmonically injection-locked frequency locked-loop, and the circuit is designed using TSMC 90 nm CMOS process. Due to the divider-less topology, it has lower dc power consumption, phase noise, and jitter. The proposed IQ modulator consists of a quadrature sub-harmonically injection-locked frequency-locked loop and four reflection-type modulators. It can be applied to the performance of various modulation methods due to its high modulation quality and wide bandwidth. Due to the low phase noise and quadrature error of the quadrature frequency-locked loop, the modulation scheme can reach up to 128 QAM. The measured 128-QAM EVM is within 3%. With a symbol rate of 3 GB/s, the measured 16-QAM is within 6%. The overall DC power number is 36.9mW. The proposed 2n-QAM IQ modulator demonstrates good performance and it can be further used in advanced millimeter-wave transmitters.
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