適用於合成孔徑雷達成像之測距都普勒演算法與硬體實作;Hardware Implementation of Range Doppler Algorithm for Synthetic Aperture Radar Imaging

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题名:	適用於合成孔徑雷達成像之測距都普勒演算法與硬體實作;Hardware Implementation of Range Doppler Algorithm for Synthetic Aperture Radar Imaging
作者:	金宏遠;Chin, Hung-Yuan
贡献者:	電機工程學系
关键词:	適用於合成孔徑雷達成像之測距都普勒演算法與硬體實作;Hardware Implementation of Range Doppler Algorithm for Synthetic Aperture Radar Imaging
日期:	2021-08-19
上传时间:	2021-12-07 13:10:24 (UTC+8)
出版者:	國立中央大學
摘要:	隨著合成孔徑雷達成像解析度的上升，大點數二維傅立葉轉換、大量的資料運算與記憶體需求、高吞吐量的資料交換都是即時成像是所必須面對的挑戰。而在合成孔徑雷達的演算法中，我們常常需要將二維時域的訊號轉到頻域來處理，例如:測距都普勒演算法、鳥鳴刻度演算法，而二維傅立葉轉換佔整體演算法的70%以上。此研究探討在不同條件下測距與方位方向的成像效率，提供一個有效率的大點數二維快速傅立葉轉換流程，對方位方向的傅立葉轉換做分解，可以增加內部記憶體對外部記憶體交換資料時使用突發模式時的長度進而增加傳輸速度，流程主要搭配平行處理8套基數為2^3的單一路徑回授架構，因此架構規律也利用管線化加速並可減少複數乘法數量，伴隨傅立葉轉換所造成的索引順序的位元反轉亦被考慮，使用原位排序緩衝器與內外部記憶體存取的方法進一步減少對於記憶體的消耗，且方位方向的快速傅立葉轉換與反轉換可以透過位元反轉索引的方式共享減少旋轉因子尋找查表用的唯讀記憶體。根據RADARSAT-1在測距都普勒演算法的資料分布，以客製化浮點數的格式在Xilinx的ultrascale系列的場域可編程邏輯閘陣列VCU128實作二維快速傅立葉轉換與反轉換，支援的成像大小為測距方向8192、16384與32768點三種，方位方向支援8192點，操作頻率在111M赫茲，影像經過二維傅立葉轉換與反轉換後的訊雜比在37.9dB以上。除二維傅立葉轉換，相位補償亦是測距都普勒演算法常用的運算之一，相位補償有三種分別是測距方向壓縮、方位方向壓縮與二次測距壓縮，我們評估並比較了複數乘法器與座標旋轉數字計算搭配在演算法中的效能與硬體資源使用，用複數乘法器做測距壓縮以配合傅立葉轉換的複數輸出；以雙精確度、客製化浮點數與定點數的混合架構完成方位方向壓縮，並以多區段二階泰勒展開簡化開根號的運算達到降低即時運算的複雜度，支援雷達斜視角0到9度、測距方向點數亦與傅立葉轉換相同支援8K到32K，訊雜比為52.7dB；硬體設計上與方位方向壓縮共享多區段二階泰勒展開的參數計算、查表的索引計算、唯讀記憶體的方式來完成二次測距壓縮，以節省硬體的使用。;With the requirements of higher resolution of Synthetic Aperture Radar (SAR) imaging, real-time computations including the large-size FFT and intensive data communications become a challenging task. Two-dimensional (2D) Fourier transform is widely used in SAR imaging algorithms, like Range Doppler Algorithm (RDA) and Chirp Scaling Algorithm (CSA). The 2D Fourier transform accounts for more than 70% of the computations in the algorithms. In this thesis, the imaging efficiency in the different conditions is first discussed. The decomposition of azimuth FFT is adopted, which increases the efficiency of communications between local memory and DRAM by the longer burst length of the burst mode. The 8 sets of radix -23 single-delay feedback architecture are used due to its regularity and pipeline nature with less complex multipliers. The in-place bit-reversal buffer and data access between DRAM and local buffer save the memory requirements. Besides, the look-up ROM tables are shared for decomposed FFT/IFFT in the azimuth direction by simple control logic. The 2D FFT/IFFT is designed with the customized floating-point format on FPGA of Xilinx ultrascale VCU128. The 2D FFT/IFFT supports 8192, 16384, and 32768 points in the range direction, and support 8192 points in azimuth direction. The frequency of the FPGA approach 111 MHz. The signal-to-quantization-noise (SQNR) of after successive 2D FFT and IFFT is above 37.9dB. Beside 2D FFT/IFFT, the phase compensation is also required in RDA. Range compression, azimuth compression and second range com-pression (SRC) are employed. We evaluate and compare the performance and utili-zation of the complex multipliers and Coordinate rotation Digital Computer (CORDIC) operations and select to use complex multipliers. The azimuth compression is com-pleted by mixed datapath formats, which consist of the double-precision float-ing-point, the customized floating-point, and the fixed-point representations. The piecewise Taylor series expansion replaces the square root operations for complexity reduction. The azimuth compression supports the radar squint angle from 0 to 9 de-grees. The signal-to-noise ratio is 52.7dB. The designs of piecewise Taylor series ex-pansion, the index computation, and the ROM tables are shared by SRC and azimuth compression for hardware reduction.
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