具資料獨立相位追蹤補償技術之20 Gb/s 半速率四階脈波振幅調變時脈與資料回復電路;A 20 Gb/s Half-Rate PAM-4 Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique

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題名:	具資料獨立相位追蹤補償技術之20 Gb/s 半速率四階脈波振幅調變時脈與資料回復電路;A 20 Gb/s Half-Rate PAM-4 Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique
作者:	柯佑諺;Ke, yuyen
貢獻者:	電機工程學系
關鍵詞:	資料與時脈回復電路;相位偵測器;抖動容忍度;高速串列傳輸;四階脈波振幅調變;Clock and data recovery;CDR;JTOL;Jitter tolerance;PAM-4;Serdes;High speed serial link
日期:	2021-09-14
上傳時間:	2021-12-07 13:13:38 (UTC+8)
出版者:	國立中央大學
摘要:	近年來，隨著科技的蓬勃發展對於傳輸速率的要求日益增加，高速串列傳輸技術取代傳統並列傳輸成為現今主流的傳輸技術。例如HDMI、Displayport、USB、SATA、PCI-Express等。此外隨著資料傳輸速率不斷的提升，為了降低系統所需的頻寬要求，四階脈波振幅調變的資料型態也逐漸被採用來取代非歸零式資料，以應付更高速的傳輸速率。本論文參考CEI-28G-VSR規格實現一個具資料獨立追蹤補償技術之半速率四階脈波振幅調變時脈與資料回復電路。提出的相位追蹤補償相位偵測器，解決傳統二進位相位偵測器在資料沒有轉態時可能造成高頻抖動容忍度降低的問題，並透過簡化相位偵測器的架構以減少迴路延遲，藉此來提高抖動容忍度的表現。為了傳遞四階脈波振幅調變訊號，本論文提出一臨界電壓自適應系統，透過對四階脈波振幅調變訊號的資料準位進行自適應收斂，再利用電阻分壓的方式收斂出合適的臨界電壓，以利於系統對四階脈波振幅調變訊號進行判斷，藉此來還原出正確的資料，並達到更大的使用彈性。本論文之實驗晶片使用TSMC 40 nm (TN40G) 1P10M CMOS製程設計，電路操作電壓為0.9 V，輸入資料為20 Gb/s四階脈波振幅調變訊號，並利用PRBS7進行編碼，還原時脈速率為5.0 GHz，還原時脈之抖動峰對峰值為8.93 pspp，方均根植為1.49 psrms，抖動容忍度於佈局前模擬中與傳統二進位相位偵測器相比則有15.63 %的改善，功率消耗為122.84 mW，晶片面積為0.96 mm2，核心電路面積為0.096 mm2。;In recent years, with the rapid development of technology, the demand for transmission rate is increasing. High Speed Serial Link Technology has replaced the parallel transmission and become the mainstream transmission technology, such as HDMI、Displayport、USB、SATA and PCI-Express. In addition, as data rates continue to increase, PAM-4 data is being used to replace NRZ data in order to reduce the bandwidth requirements of the system to meet higher data rate. This thesis refers to the CEI-28G-VSR specification and presents a half rate PAM-4 clock and data recovery (CDR) with data independent phase tracking compensation technique. The proposed phase tracking compensation phase detector (PTCPD) solves the problem that the conventional bang-bang phase detector (BBPD) may reduce the high frequency jitter tolerance (JTOL) when the input data has long run situation. In addition, by removing the re-timing circuit of the BBPD to reduce the loop latency, the JTOL can be improved. In order to transmit the PAM-4 signal, this thesis presents a threshold voltage adaptive system. This system will adaptively converge the reference levels of the PAM-4 signal. Then, the resistors are used to divide the appropriate threshold voltage for the CDR to detect the PAM-4 signal. With this adaptive system, the PAM-4 CDR can achieve greater flexibility in use. This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process with 0.9 V supply voltage and the data rate is 20 Gb/s PRBS7 PAM-4 signal. The recovered clock is 5.0 GHz. The simulated jitter of the recovered clock is 8.93 pspp and 1.19 psrms. In pre-layout simulation, 15.63% improvement in jitter tolerance compared to conventional BBPD. The total power consumption is 122.84 mW, chip area is 0.96 mm2 and the core area is 0.096 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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