| 摘要: | 在有線通訊中，由於雙絞線全雙工傳輸的迴音干擾現象，接收端之訊號與雜訊比受到嚴重影響，顯示了迴音消除器之必要性。傳統上迴音消除方法為使用自適應濾波器，複製迴音路徑之通道效應，使得訊號經過迴音路徑與訊號經過迴音消除器相同，進而將迴音扣除。一般高成本之作法為使用有限脈衝響應 ( Finite Impulse Response, FIR ) 濾波器，隨著通道效應拉長，有限脈衝響應濾波器需跟著拉長才能達到可接受之回音扣除效果，意即需要之乘法器數量也會隨之增長，造成電路成本提高，因此在有達到性能要求之模擬結果下，降低電路成本越來越受到重視。本論文所採用之迴音通道模型，在尾段的部分有因為近端 ( Near end ) 與遠端 ( Far end ) 傳輸不匹配所造成小幅度之反射波 ( Reflection ) ，且反射波位置會因通道長度而有所改變，因此使得現存一些文獻所提出之方法無法達到期望之迴音扣除效果，抑或是電路成本無法大幅改善。本論文除了將文獻所提供之方法混和 ( Hybrid ) 有限脈衝響應 ( FIR ) 無限脈衝響應 ( Infinite Impulse Response, IIR ) 濾波器與插植濾波器 ( Interpolator filter ) 進行模擬分析，並針對所使用之迴音通道提出改良之架構，使得迴音扣除效果在要求範圍內，電路成本之節省相較於傳統使用有限脈衝響應濾波器達到超過70%的效果，且對使用插值濾波器，與改良之混和有限脈衝響應與無限脈衝響應濾波器，也有59%與11%之節省。關於硬體實現，使用Verilog HDL描述與模擬，透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，再經由Design compiler與IC compiler來驗證在製程為TSMC-40nm下之電路功能。;In wireline communications, the signal-to-noise ratio at the receiving end is affected by the echo interference of twisted-pair full-duplex cables transmission. In order to realize the necessary of echo canceller, the traditional method of echo cancellation uses an adaptive filter to copy the echo channel effect, so that signal passes through the echo path is the same as that passes through the echo canceller, and then the echo is subtracted. In the literature, high-cost method is to use Finite Impulse Response (FIR) filter. Along with channel effect becomes longer, the finite impulse response filter needs to be elongated to achieve an acceptable performance, which means the number of multipliers required. It will also result in an increase of cost. Therefore, with the acceptable performance, reducing circuit cost is more and more important.
In this work, in addition to simulate the methods provided in the literature which called the Hybrid FIR-IIR (Infinite Impulse Response) filter, and Interpolation filter, we also proposed an improved method which can still maintain the required performance, and compared it with the traditional method that used FIR filter, the circuit cost saving can reach more than 70%, as for comparing with Interpolation filter, and Hybrid FIR-IIR filter, there are also 59% and 10% saving.
Regarding the hardware implementation, first the Verilog HDL description is employed and the related simulations ,are conducted, then verify the circuit function through SMIMS VeriEnterprise Xilinx FPGA, and finally verify the circuit function under the TSMC-40nm process through Design Compiler and IC Compiler. |
