在多樣態的晶圓圖中找尋隱藏的刮痕樣態;Hidden Scratch Pattern Recognition In Multiple Type

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题名:	在多樣態的晶圓圖中找尋隱藏的刮痕樣態;Hidden Scratch Pattern Recognition In Multiple Type
作者:	張凱程;Cahng, Kai-Cheng
贡献者:	電機工程學系
关键词:	晶圓圖;錯誤樣態辨識;特徵分析;Wafer map;Defect type recognition;Feature based analysis
日期:	2022-01-22
上传时间:	2022-07-14 00:23:59 (UTC+8)
出版者:	國立中央大學
摘要:	隨著半導體產業的興盛，晶圓圖分析是一個相當重要的議題，藉由分析晶圓圖上的錯誤樣態，可以知道哪道製程有問題產生，並針對不同的根本原因對機台做調整，例如:探針測試中，可能會因為測試探針在經過多次測試後有沾黏一些東西，導致測試時探針無法與待測晶片的接點有效地接觸，使得測試資料無法正確輸入到電路中測試，讓測試結果為壞品。本篇論文主要以特徵分析的方式，針對刮痕的錯誤樣態進行辨識與分析，利用霍夫轉換為基礎提出一套辨識模型，來判斷晶圓圖上是否有直線和弧線的缺陷，使用的實際晶圓圖為台積電所提供的WM-811K晶圓資料庫，其中的錯誤樣態可分為以下九種，Center、Donut、Scratch、Edge-Ring、Edge-Loc、Loc、Near-Full、Random、None。最後在WM-811K中取部分作為測試資料，以準確率、精確率、召回率的數值表現來顯示本論文模型的判斷準確度，基於此模型下，針對單樣態的刮痕辨識準確率能達到95.45%，多樣態的刮痕辨識準確率為76.21%，運算時間約3.92 ms/wafer 。;With the prosperity of the semiconductor industry, wafer map analysis is a very important issue. By analyzing the wafer map defect patterns, we can know the corresponding process problems and adjust the machine at different root causes, for example: in chip probing, test probe may stick something after multiple tests, which may cause the probe cannot effectively contact the pad of the test wafer, and lead to the test patterns may not be correctly input into the test circuit, that let the test result be bad. This paper mainly uses Feature-base analysis to identify and analyze the scratch defect pattern, and use Hough transform to propose a identification model to decide whether have line or arc defects on the wafer map. The actual wafer map we used is WM-811K wafer database provided by TSMC. The defect patterns can be divided into the following nine types: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near- Full, Random, None. Finally, take part of WM-811K as the test data, and use the numerical performance of Accuracy, Precision, and Recall to show the classification accuracy of the model in this paper. Based on this model, Single type scratch recognition accuracy could achieve 95.45%, Multiple type scratch recognition accuracy is 76.21%. Calculation time cost is about 3.92 ms/wafer.
显示于类别:	[電機工程研究所] 博碩士論文

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