應用於第五代通訊之互補式金氧半導體F23類考畢茲壓控振盪器與變壓器回授轉導提昇壓控振盪器暨整數型鎖相迴路之研製;Implementations on CMOS Class-F23 Colpitts Voltage Controlled Oscillator, Transformer Feedback Gm Boosting Voltage-Controlled Oscillator, and Integer-N Phase-Locked Loop for 5G Communications

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題名:	應用於第五代通訊之互補式金氧半導體F23類考畢茲壓控振盪器與變壓器回授轉導提昇壓控振盪器暨整數型鎖相迴路之研製;Implementations on CMOS Class-F23 Colpitts Voltage Controlled Oscillator, Transformer Feedback Gm Boosting Voltage-Controlled Oscillator, and Integer-N Phase-Locked Loop for 5G Communications
作者:	張貽閔;Chang, Yi-Min
貢獻者:	電機工程學系
關鍵詞:	變壓器;F23類;轉導提升;考畢子;壓控振盪器;transformer;class F23;Gm boosted;colpitts;VCO
日期:	2022-08-27
上傳時間:	2022-10-04 12:10:24 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文擬研究收發機中本地振盪源的相關電路，設計應用於第五代行動通訊(5th Generation Wireless Systems)之n79頻段本地振盪電路，本論文首先針對振盪條件進行介紹，接下來針對相位雜訊的成因進行分析與探討，並且針對flicker noise upconversion對相位雜訊的貢獻找出解決方法，實作並分析F類之優缺點，並針對F類直流功耗較大進行優化，接著使用變壓器回授實作壓控振盪器並分析其優缺點，針對直流功耗進一步優化，並進一步將變壓器回授轉導提升壓控振盪器接成整數型所相迴路，針對所相迴路各子電路進行分析，進一步對迴路進行整體迴路分析，實作出C頻段整數型所相迴路，最後實現低功耗、低相位雜訊的整數型鎖相迴路，論文一共實現三種電路，皆使用tsmcTM 0.18 μm互補式金氧半導體製程製作，內容如下所述： 1. F_23類考畢茲壓控振盪器本電路實作具有低相位雜訊特性之F_23類控振盪器，使用變壓器耦合實作F_23類共振腔，並獨立主、副線圈並利用中心抽頭偏壓優化直流功耗，再利用考畢茲進一步實現更低的直流功耗，整體電路功耗為 5.3 – 4.5 mW，可調頻寬為 4.36 – 5.04 GHz (14.37%)，相位雜訊在 1-MHz 偏移頻率下最低為−122.1 dBc/Hz，達到 FoM最高為−188.9 dBc/Hz，晶片面積為 0.737×1.1 mm2，整體電路換算之電路優化指標仍具競爭力。 2. 變壓器回授轉導提昇壓控振盪器本電路實作具有低功耗、低相位雜訊，使用變壓器回授與轉導提升降低公耗與相位雜訊，整體電路功耗從7.14 ~ 7.32 mW，可調頻寬為 4.43 – 4.82 GHz (16.3%)，相位雜訊在 1-MHz 偏移頻率下最低為−118.9 dBc/Hz，達到 FoM最高為−184.5 dBc/Hz，晶片面積為 0.694×1.23 mm2，本設計負電組效果較差，與多數文獻相比具有不錯的特性表現。 3. 利用變壓器回授轉導提昇壓控振盪器於C頻整數型鎖相迴路本電路利用變壓器回授轉導提昇壓控振盪器，實現整數型C頻段鎖相迴路，於章節中完整介紹各子電路之用途及數學分析，整體電路功耗為33.9 mW，最後利用雜訊轉移函數計算整體系統之相位雜訊，得到的相位雜訊在1 MHz位移下為102.5 dBc/Hz，晶片面積為0.905×1.368 mm2。雖然尚未進行量測，但可獲得許多關於整數型鎖相迴路設計上之經驗。 ;This thesis investigates the designs of the local oscillators for the applications in n79 band of the fifth-generation mobile communication (5th Generation Wireless Systems), Firstly, we introduce the oscillation condition, analyze the causes of phase noise, find the solution for the contribution of flicker noise up conversion to phase noise, then implement the transformer feedback Gm Boosting Class-F voltage-controlled oscillator (VCO). The advantages and disadvantages of the this VCO were analyzed and optimized its performance, including phase noise and DC power consumption. Then, the designed VCO was used as a sub-circuit in a C-band integer-N phase locked loop. All circuits were implemented in tsmcTM 0.18-μm CMOS technology. 1. A Class-F_23 Colpitts Voltage Controlled Oscillator Class-F_23 oscillator features the high power efficiency and low phase noise. In this work, we used transformer coupling technique to realize Class-F_23 LC-tank, and separate the center tape of the primary and secondary coils. The DC power consumption was optimized as low as 5.3 - 4.5 mW in this Class-F Colpitts VCO. The measured results are achieved as follow, the tuning range is 4.63 - 5.04 GHz (14.37 %), the lowest phase noise at 1-MHz offset frequency is -122.1 dBc/Hz which is correspondent to the FoM of -188.9 dBc/Hz. The chip size included pads is 0.737×1.1 mm2. 2. A Transformer Feedback Gm Boosting Voltage-Controlled Oscillator The transformer feedback Gm boosting VCO features the low power consumption and low phase noise. In this work, we use transformer coupling technique to realize large output power, and adopt Gm boosting technique to reduce the power consumption. The DC power consumption was optimized as low as 7.14 -7.32 mW. The measurements achieve a tuning range of 4.43 - 4.82 GHz (16.3 %), and a phase noise at 1-MHz offset frequency of -118.9 dBc/Hz which is correspondent to the FoM of −184.5 dBc/Hz. The chip size included pads is 0.694×1.23 mm2. 3. A C-band Integer-N PLL with Transformer Feedback Gm Boosting Voltage-Controlled Oscillator The PLL adopted the previously developed transformer feedback Gm boosting VCO to improve the phase noise performance. This analytical the mathematical model of the charge pump phase-locked loops (CPPLL). The noise contributions of each component in PLL were studied and compared. Meanwhile, we also calculate the overall phase noise of the PLL by using noise transfer function. The PLL consumed the DC power of 33.9 mW, The chip size included all pads is 0.905 × 1.368 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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