堆疊式矽鍺奈米片場效電晶體用於3奈米之先進製程技術;Utilizing Stacked SiGe Nanosheets FET in Advanced 3 Nanometer Process Technology

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題名:	堆疊式矽鍺奈米片場效電晶體用於3奈米之先進製程技術;Utilizing Stacked SiGe Nanosheets FET in Advanced 3 Nanometer Process Technology
作者:	鄭雄;Cheng, Hsiung
貢獻者:	機械工程學系
關鍵詞:	原子層沉積;高介電常數;四甲基氨氫氧化合物;金屬閘極;Atomic Layer Deposition;High-K;Tetramethylammonium hydroxide;Metal gate
日期:	2024-06-07
上傳時間:	2024-10-09 17:17:45 (UTC+8)
出版者:	國立中央大學
摘要:	原子層沉積(Atomic Layer Deposition, ALD)製程已被用於沉積在高介電常數(High-K)材料，例如氧化釔(Y2O3)，其介電常數相對於二氧化矽較高，這表示在相同的電場下，氧化釔能夠儲存更多電荷進而提高其電容值，也因為具備較高的電容值就具有較佳的絕緣效果，因此其適合作為奈米元件之閘極絕緣層。故本研究在實驗中將使用不同氧化物成長於矽基材，並探討其電性及氧化物與基材間的物理特性。最後，利用原子層沉積製程技術來沉積薄膜層用來製作元件的絕緣層，製造出3奈米世代的矽鍺半導體元件。本研究中展示的元件製造，其涉及的關鍵製程技術是採用低壓化學氣相沉積矽/矽鍺多層磊晶、並使用四甲基氨氫氧化(Tetramethylammonium hydroxide, TMAH)溶液選擇性蝕刻矽鍺層上的矽層並使用氧化釔作為閘極介電層之金屬閘極進行原子層沉積，所製造的通道長度為180 nm 的堆疊式矽鍺奈米片p 型場效應電晶體，透過電性測量確認ION/IOFF 比約為1×105 以及次臨界擺幅為130 mV/dec。此外，由於其高品質的氧化釔閘極介電層，該裝置表現出極小的漏極誘發降低現象。這些設計可以提高通道的閘極可控性和裝置特性。本研究展示了使用矽/矽鍺多層的堆疊式矽鍺奈米片p 場效應電晶體成功開發矽鍺製程選擇性蝕刻以獲得矽鍺奈米片，其堆疊式矽鍺奈米片環繞式閘極場效電晶體滿足超越3 奈米技術節點以及更高要求之潛力。 ;Atomic Layer Deposition (ALD) process has been employed for depositing high-k dielectric materials, such as yttrium oxide (Y2O3). Its dielectric constant is igher than that of silicon dioxide (SiO2), indicating that under the same electric field, yttrium oxide can store more charge, thereby increasing its capacitance. Due to its higher capacitance, it exhibits superior insulating properties, making it suitable as the gate insulating layer for nanoscale devices. In this research, different oxides will be grown on germanium substrates in the experiments, and the electrical properties and physical characteristics between the oxides and the germanium substrate will be discussed. Finally, utilizing the atomic layer deposition process to stack insulating layers for device isolation, aiming to manufacture 3 nanometer generation germanium semiconductor devices. In this paper, the key process technologies involved in the fabrication of the device include low-pressure chemical vapor deposition for SiGe/Si multilayer epitaxy, using a wet solution of tetramethylammonium hydroxide for the selective etching of silicon layers over silicon germanium layers, and atomic layer deposition of a high-k dielectric material for the gate dielectric of the metal gate. For the manufactured stacked SiGe NS p-GAAFETs with a channel length of 180nm, the ION/IOFF ratio of approximately 1.0 × 105 and a subthreshold swing of 75 mV/dec were validated via electrical measurements. Furthermore, due to the highquality of the Y2O3 gate dielectric, the device exhibited a minimal drain-induced barrier-lowering effect. These designs can enhance the control of the gate over channel and device characteristics.
顯示於類別:	[機械工程研究所] 博碩士論文

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