| 摘要: | 提高GaN-on-Si元件的崩潰電壓是一個重要的設計考量，本實驗採用了相對較厚(6.5 μm)的碳摻雜緩衝層作為磊晶的一部分，並生長在低阻值的矽基板上。通過閘汲間距(LGD)尺寸的評估和公式推導，預測元件的尺寸和崩潰電壓的關係。利用Silvaco TCAD軟體對不同閘汲間距元件進行電性分析和崩潰電壓預測，並在此磊晶結構上製作出加強型氮化鎵閘極電晶體以進行量測分析和比較。後續並探討了不同緩衝層厚度對崩潰電壓的影響，以期能了解GaN-on-Si的磊晶緩衝層對不同崩潰電壓規格的關係，進而得到適當元件結構及減少磊晶成本。
不同閘汲間距的p-GaN gate AlGaN/GaN HEMTs元件，在矽基板接地的設定下進行崩潰電壓量測。當LGD = 8 μm時，元件在汲極漏電流達1 mA/mm時的崩潰電壓為1298 V，LGD = 11 μm則為1742 V，其特徵導通電阻(RON,SP)分別為1.55 m∙cm2和 1.77 m∙cm2。通過觀察汲極、閘極和垂直方向的緩衝層基板漏電流，發現在LGD = 8 μm的設計中，崩潰電壓的主要限制並非來自垂直方向的緩衝層基板漏電流，原因是由於閘汲間距短，使緩衝層厚度的漏電流影響變成非影響崩潰電壓的主因，而在LGD = 11 μm的元件中，垂直方向的緩衝層基板漏電流則成為崩潰電壓的主要限制因素。同時也觀察實驗室之前的製程元件，在LGD > 11 μm的元件中，垂直方向的緩衝層基板漏電流確認為崩潰電壓的主要限制因素。
雖然此實驗主要採用6.5 μm的碳摻雜緩衝層為製程晶片，但最後利用Silvaco TCAD軟體進行不同緩衝層厚度對崩潰電壓的分析，在使用相同元件結構設計(LGD = 8 μm)，並以維持1200 V崩潰電壓的前提下，對不同緩衝層厚度進行研究。根據模擬結果，緩衝層厚度可從本實驗所使用之6.5 μm縮減至4.5 μm，仍然在汲極漏電流定義在1 mA/mm時，達到1251 V的崩潰電壓。;Improving the blocking voltage of GaN-on-Si devices is an important design consideration. In this experiment, a relatively thick (6.5 μm) carbon-doped buffer layer was used as part of the epitaxial structure, grown on a low-resistivity silicon substrate. By estimating the gate-drain distance (LGD) dimension and formula derivation, the relationship between device size and blocking voltage was observed. Using Silvaco TCAD simulation, the electrical characteristics and blocking voltage prediction of devices with different gate-drain distances were analyzed. Enhancement-mode GaN gate transistors were then fabricated on this epitaxial structure for measurement and analysis. The impact of different buffer layer thicknesses on the blocking voltage was investigated, in order to understand the relationship between the GaN-on-Si epitaxial buffer layer and the blocking voltage specifications, and to obtain the appropriate device structure and reduce manufacturing costs.
p-GaN gate AlGaN/GaN HEMTs devices with different gate-drain distances were measured for off-state blocking voltage under silicon substrate conditions. When LGD = 8 μm, the device exhibited a blocking voltage of 1298 V at a drain leakage current of 1 mA/mm, and when LGD = 11 μm, the blocking voltage was 1742 V, with corresponding specific on-resistance (RON,SP) values of 1.55 mΩ·cm2 and 1.77 mΩ·cm2, respectively. By observing the drain, gate, and vertical substrate leakage currents, it was found that for the LGD = 8 μm design, the primary limitation on blocking voltage was not the vertical buffer substrate leakage current, likely due to the short gate-drain distance. In contrast, for the LGD = 11 μm design, the vertical buffer substrate leakage current became the main limiting factor for the blocking voltage. Previous experiments also confirmed that for devices with LGD larger than 11 μm, the vertical buffer substrate leakage current was the primary limitation for the blocking voltage.
Although this experiment primarily used a 6.5 μm carbon-doped buffer layer, Silvaco TCAD simulations were ultimately performed to analyze the impact of different buffer layer thicknesses on the blocking voltage. Using the same device structure design (LGD = 8 μm) and maintaining a 1200 V blocking voltage, the study was conducted for various buffer layer thicknesses. The simulation results showed that the buffer layer thickness could be reduced from the 6.5 μm used in this experiment to 4.5 μm, while still achieving a 1251 V blocking voltage at a drain leakage current of 1 mA/mm. |
