English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 78852/78852 (100%)
造訪人次 : 38478405      線上人數 : 253
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋


    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/9785


    題名: 快速響應反脈衝式電鍍電源系統之研製;Design and implementation of fast response for reverse-pulse plating power system
    作者: 張芳林;Fang-Lin Chang
    貢獻者: 電機工程研究所
    關鍵詞: PD控制;CPLD;反脈衝式電鍍;PD control;CPLD;reverse-pulse plating
    日期: 2004-07-02
    上傳時間: 2009-09-22 11:56:07 (UTC+8)
    出版者: 國立中央大學圖書館
    摘要: 傳統電鍍皆使用直流電源進行,而電鍍通孔的孔壁無法達到均勻銅厚品質,且其過程相當耗電以及耗材料,因此本論文進行快速響應反脈衝式電鍍電源系統之研製,其主要目的是產生快速轉態反脈衝輸出電流,以供給電源給印刷電路板做電鍍通孔之用,使得通孔的孔內壁與板面的鍍銅厚度趨近1:1,並且可減少電鍍時間、改善電鍍之銅層品質與增加印刷電路板之產能。 反脈衝式電鍍電源輸出主要是利用功率級電路-全橋式轉換器實現,並且搭配CPLD控制IC做為系統控制核心,系統控制採全數位化控制。其中控制IC內部包括PWM產生、取樣命令產生、鍵盤掃描、七段顯示器掃描以及控制演算法實現…等模組化電路。本系統中可進行反脈衝電流控制與電流時間比調變。 為了得到良好的反脈衝電流響應,本論文設計一比例微分控制器來改善系統性能,進而滿足系統規格。並且透過模擬驗證控制器的可行性,再以實際硬體測試結果來驗證其效能,藉以佐證快速響應反脈衝式電鍍電源系統之可行性與實用性。 在本電鍍電源系統中,具有週期性反脈衝電流輸出:正20安培/負200安培,上升時間小於100微秒(us),因此可知,本論文所設計之系統確實可實現快速轉態反脈衝輸出電流,且可應用於印刷電路板產業。 In the traditional plating, the direct current was used to be the power supply. But the thickness of the internal wall of the plating through hole could not be plated uniformly, and the process of plating always consumed the electricity and materials. Therefore, a fast response for reverse-pulse plating power system is designed in this thesis. The purpose of this system is to produce the fast dynamic reverse-pulse output current as the plating power supply. So the ratio of copper-plating thickness between the internal wall of the plating through hole and the surface of the printed circuit board tends to one. This system also reduces the plating time, improves the copper-plating quality and increases the quantity of producing printed circuit board. The reverse-pulse plating power system is realized by the full-bridges converter. The system is fully digitalized and the control kernel of the system is implemented by CPLD. This system can control the reverse-pulse current and modulate the ratio of current time. In order to obtain a desirable current response, a proportional-derivative controller is designed to improve the system performance and then satisfy the system specification. The simulation results confirm the feasibility of the controller and the experimental results further demonstrate the dynamic performance. The output range of periodic reverse-pulse current in the experimental system is between 20 A positive and 200 A negative. The rise time is less than 100 microseconds. Therefore, this system actually can realize the fast dynamic reverse-pulse output current.
    顯示於類別:[電機工程研究所] 博碩士論文

    文件中的檔案:

    檔案 大小格式瀏覽次數


    在NCUIR中所有的資料項目都受到原著作權保護.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明