摘要(英) |
As the evolution of semiconductor process technology from 0.18um, 90nm to the present minimum is 22nm, the process variation will be more and more serious in device mismatch. This represents the analog circuit design increase time-consuming and high complex, then layout automation is likely to play a key role in analog circuit design. The performance of many types of analog circuits, like ADC, DAC, filter, etc., relies on the implementation of accurate capacitor array ratios. In order to reduce the negative effects, designers are determined by properly arranging the identical unit-size capacitors and used spatial correlation to decrease the effect of process variation. Among them, how many unit-size capacitor you want to cut and how to assign the capacitance in capacitor array has become a very important part with automatic layout assignment.
In this thesis, we propose a layout assign method a yield-aware placement with power-of-two cutting and weighted priority for capacitor array block creator. We place by changing the priority of capacitor according to different circuit constraints, the placement will be place in a better result. And we have established a power-of-two matrix structure, and propose a power-of-two capacitance cutting method. Used this method in the capacitor placement can achieve high dispersion, less time-consuming and the accuracy of capacitor array layout. Finally, we cite a few different placements to illustrate the impact of placing the array. For a particular circuit, various assignment capacitor arrays are validated by their circuit yield, which is done by Monte Carlo method. The results show the matching of capacitor ratio increased and the circuit yield enhancement. |
參考文獻 |
[1] X. Jinjun, V.Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr. 2007.
[2] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[3] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. Solid-State Circuits, pp.611-616, May 1994.
[4] P-W. Lou, J-E. Chen, C-L Wey, L-C. Cheng, J-J. Chen, and W-C. Wu, ”Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, Iss. 11, pp. 2097-2101, Nov. 2008.
[5] D. Sayed and M. Dessouky, “Automatic generation of common-centroid arrays with arbitrary capacitance ratio,” in Proc. Design Autom. Test Eur.Conf. Exhibit., pp. 576–580, Mar. 2002.
[6] J.-E Chen, P.-W. Luo, and C.-L. Wey, “Placement optimization for yield improvement of switched-capacitor analog integrated circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 2, pp. 313-318, Feb. 2010.
[7] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” in Proc. ACM/IEEE DAC, 2011, pp. 528-533.
[8] C.L. Wey, J.E. Chen, C.-C. Huang, and P.-W. Luo, “Yield-Driven Common-Centroid Capacitor Placements for Mixed-Signal/Analog Integrated Circuits,” Proc. of Int’l Workshop on Design Automation on Analog/Mixed-signal Integrated Circuits, San Jose, CA, Nov. 8, 2012.
[9] D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline, and H. Ragai, “Evaluation of Capacitance Ratios in Automated Accurate Common-Centroid Capacitance Arrays,” Proceedings of the 6th ISQED, March 2005, pp. 143-147.
[10] H. Masuda, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes,” IEEE Custom Integrated Circuits Conference 2005.
[11] L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithm in analog-layout designs,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp.1889-1903, Oct. 2006.
[12] M.-F. Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuit and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
[13] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp.1433-1439, Oct 1989.
[14] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
[15] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989
[16] K.R. Laker and W.M. Sansen, Design of Analog Integrated Circuits and Systems, McGraw Hill, 1994. |