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    Items for Author "Cheng,KH" 

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    Showing 13 items.

    Collection Date Title Authors Bitstream
    [電機工程研究所] 期刊論文 2003 A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop Cheng,KH; Yang,WB; Ying,CM
    [電機工程研究所] 期刊論文 2004 A fast-lock DLL with power-on reset circuit Cheng,KH; Lo,YL; Jiang,SY
    [電機工程研究所] 期刊論文 2004 A low-power high-driving ability voltage control oscillator used in PLL Cheng,KH; Yang,WB; Chung,CF
    [電機工程研究所] 期刊論文 2005 64-bit high-performance power-aware conditional carry adder design Cheng,KH; Cheng,SW
    [電機工程研究所] 期刊論文 2006 64-bit pipeline carry lookahead adder using all-N-transistor TSPC logics Cheng,KH; Cheng,SW; Lee,WS
    [電機工程學系] 期刊論文 2010 A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications Cheng,KH; Tsai,YC; Wu,YH; Lin,YF
    [電機工程學系] 期刊論文 2010 Dynamic frequency tracking and phase error compensation clock de-skew buffer Cheng,KH; Hong,KW; Lo,YL; Wu,CL; Lee,CH
    [電機工程學系] 期刊論文 2011 A 0.5-V 0.42.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip Cheng,KH; Tsai,YC; Lo,YL; Huang,JS
    [電機工程學系] 期刊論文 2011 A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique Cheng,KH; Hung,CL; Chang,CH
    [電機工程學系] 期刊論文 2011 A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler Cheng,KH; Liu,JC; Huang,HY; Li,YL; Jhu,YJ
    [電機工程學系] 期刊論文 2011 A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit Cheng,KH; Hong,KW; Chen,CH; Liu,JC
    [電機工程學系] 期刊論文 2011 Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator Cheng,KH; Liu,JC; Chang,CY; Jiang,SY; Hong,KW
    [電機工程學系] 期刊論文 2011 Fast-Write Resistive RAM (RRAM) for Embedded Applications Sheu,SS; Cheng,KH; Chiang,PC; Lin,WP; Lee,HY; Chen,PS; Chen,YS; Wu,TY; Chen,FT; Su,KL; Kao,MJ; Tsai,MJ; Chang,MF

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