隨著半導體製程的縮小，製程變動的問題是無法避免的。在晶圓製造過程中，所有元件經過相同的物理程序，因此參數變動會有某種程度的空間相關，較靠近的兩元件會有較小的參數變動。在類比電路自動化佈局中，則使用空間相關性來決定元件最佳的擺放位置，並依照繞線方式來增進所要求的匹配參數。本論文將提出兩種繞線Via-Less Channel Routing (VLCR)和Balanced-Via Channel Routing (BVCR)來完成佈局設計，並以一個陣列MiM電容的範例來展示通道繞線的成果。實驗過程中，先以Calibre來提取寄生參數再結合SPICE模擬不同電容比值、區段的情況。藉由模擬結果得知，在擺放位置決定之後，繞線將會帶來5％的不匹配，進而對效能有極大的影響。 As semiconductor technology continues to shrink, the problem of process variation is inevitable. The parameter variations should have certain spatial correlations during IC manufacturing process because all of devices are made from the common physical process. It is the closer the less for the spatial correlation of two devices. In analog-circuit layout automation, it is to determine the best layout placement of devices by considering spatial correlation and decide, in turn, the routing styles for improving the matching of desired parameters. In this thesis, two routing styles, via-less channel routing (VLCR) and balanced-via channel routing (BVCR), are proposed for completing the layout design. An example of array-type MiM capacitors is used to demonstrate the performance of the proposed channel router. In the experiment, the cases of different capacitance ratios in different segment units are considered and the evaluation of post-simulation is performed by SPICE conjunction with the parasitic parameter extractor Calibre. From the result, it is observed that routing might contribute extra up to 5 percent of mismatch after the placement determined. Routing results in the great effect on the desired performance.
