An all-digital clock synchronization buffer with one cycle dynamic synchronizing

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/106580

Title:	An all-digital clock synchronization buffer with one cycle dynamic synchronizing
Authors:	鄭國興;Cheng, Kuo-Hsing;Hong, Kai-Wei;Hsu, Chi-Fa;Jiang, Bo-Qian
Contributors:	資訊電機學院電機工程學系
Keywords:	Applied sciences;Arbitrary duty cycle;clock synchronization buffer (CSB);Clocks;Delay;Design. Technologies. Operation analysis. Testing;Electronics;Exact sciences and technology;fast locking;Integrated circuits;one cycle dynamic locking;Power demand;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Synchronization;synchronous mirror delay (SMD);Tuning
Date:	2012-01-01
Issue Date:	2026-04-23 13:29:24 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
Abstract:	摘要： This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a modified fine-tuned circuit. The chip is fabricated using a 130-nm standard CMOS process. Its operating frequency range is between 300 MHz and 800 MHz. The power consumption and RMS jitter are 2.4 mW and 2.25 ps at 800 MHz, respectively. The active area of this chip is 0.015 mm 2 . 其他題名： TVLSI 出版者： New York, NY: IEEE 出版日期： 2012-10-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2012-10, Vol.20 (10), p.1818-1827 資源來源： IEEE Electronic Library (IEL) 版權： 2015 INIST-CNRS 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2011.2166092 識別號： CODEN: IEVSE9
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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