Springer Verlag;Berlin/Heidelberg: Springer Berlin Heidelberg
摘要:
摘要： In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems. 其他題名： J Real-Time Image Proc 出版者： Berlin/Heidelberg: Springer Berlin Heidelberg 出版日期： 2015-06-01 出處： Journal of real-time image processing, 2015-06, Vol.10 (2), p.193-206 版權： Springer-Verlag Berlin Heidelberg 2013 版權： Springer-Verlag Berlin Heidelberg 2013. 識別號： ISSN: 1861-8200 識別號： EISSN: 1861-8219 識別號： DOI: 10.1007/s11554-013-0324-7
