Institution of Engineering and Technology;The Institution of Engineering and Technology
摘要:
摘要： This study proposes a post-distortion linearisation technique for 5 and 60 GHz complementary metal–oxide–semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP1dB) and power-added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmcTM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP1dB and saturated power (Psat) is <0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm2. The PA achieves a 14.8 dB gain, a 16.8 dBm OP1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP1dB and Psat is <0.3 dB. The linearised 60 GHz PA improves the OP1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser. 出版者： The Institution of Engineering and Technology 出版日期： 2016-03-19 出處： IET microwaves, antennas & propagation, 2016-03, Vol.10 (4), p.464-470 資源來源： Wiley Online Library (Open Access collection) 版權： The Institution of Engineering and Technology 版權： 2016 The Institution of Engineering and Technology 識別號： ISSN: 1751-8725 識別號： EISSN: 1751-8733 識別號： DOI: 10.1049/iet-map.2015.0530
