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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/107715


    題名: Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers
    作者: 李進福;Huang, Yu-Jen;Li, Jin-Fu
    貢獻者: 資訊電機學院電機工程學系
    關鍵詞: Applied sciences;Built-in self-test;built-in self-test (BIST);Design. Technologies. Operation analysis. Testing;Diagnosis;Electronics;Exact sciences and technology;IEEE 1500;Integrated circuits;Integrated circuits by function (including memories and processors);multi-port RAM;Rams;Random access memory;random access memory (RAM);Reduction;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Simulation;System-on-a-chip;system-on-chip (SOC);Test times;Testing, measurement, noise and reliability;Very large scale integration
    日期: 2012-01-01
    上傳時間: 2026-04-23 14:22:46 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
    摘要: 摘要: This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.
    其他題名: TVLSI
    出版者: New York, NY: IEEE
    出版日期: 2012-11-01
    出處: IEEE transactions on very large scale integration (VLSI) systems, 2012-11, Vol.20 (11), p.2123-2127
    資源來源: IEEE Electronic Library (IEL)
    版權: 2015 INIST-CNRS
    版權: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2012
    識別號: ISSN: 1063-8210
    識別號: EISSN: 1557-9999
    識別號: DOI: 10.1109/TVLSI.2011.2165568
    識別號: CODEN: IEVSE9
    顯示於類別:[電機工程學系] 期刊論文

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