Institute of Electrical and Electronics Engineers Inc.;IEEE
摘要:
摘要： In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment, or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor-based heuristic. 其他題名： TCAD 出版者： IEEE 出版日期： 2015-04 出處： IEEE transactions on computer-aided design of integrated circuits and systems, 2015-04, Vol.34 (4), p.577-588 資源來源： IEEE Xplore (NTUSG) 識別號： ISSN: 0278-0070 識別號： EISSN: 1937-4151 識別號： DOI: 10.1109/TCAD.2014.2385759 識別號： CODEN: ITCSDI
