Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications. 其他題名： TED 出版者： New York: IEEE 出版日期： 2014-10 出處： IEEE Transactions on Electron Devices, 2014-10, Vol.61 (10), p.3448-3455 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Oct 2014 識別號： ISSN: 0018-9383 識別號： EISSN: 1557-9646 識別號： DOI: 10.1109/TED.2014.2348856 識別號： CODEN: IETDAI
