鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製 ; Ge QD SONOS nonvolatile Floating-dot transistors

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Title:	鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製;Ge QD SONOS nonvolatile Floating-dot transistors
Authors:	曾柏皓;Po-Hao Tseng
Contributors:	電機工程研究所
Keywords:	記憶體;memory
Date:	2010-07-14
Issue Date:	2010-12-09 13:51:55 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文主要是將不同鍺莫爾濃度之多晶矽鍺沉積至氮化矽層上，再利用選擇性平面氧化多晶矽鍺的方法形成不同尺寸大小的鍺量子點，並控制氧化條件將鍺量子點嵌入至氮化矽層內，形成SONOS 記憶體與鍺量子點結合的混合式 (hybrid) 記憶體元件。藉由此混合式記憶體元件，我們預期將可增進傳統SONOS 記憶體之寫入與抹除效率、記憶體窗口以及資料保存能力等記憶體特性。此外，利用氮化矽材料分離的缺陷及浮點儲存層的特性，也可以抑制傳統浮閘記憶體的側向漏電流問題，進而降低穿隧介電層的厚度，增進元件的寫入與抹除速度以及元件耐用性。再者，此元件結構及製程不僅簡單，更與現在CMOS 的製程完全相容。In this thesis, we have fabricated hybrid memory cells incorporating Ge quantum dots(QDs) into silicon/oxide/ nitride/oxide/silicon (SONOS) for nonvolatile memory application.Ge QDs are generated by thermally oxidizing poly-Si1-xGex, and their size is tunable by Ge content in poly-Si1-xGex and thermal oxidation condition. We expected the Ge QD SONOS hybrid memory cells provide better program /erase speed, memory window, and data retention than conventional SONOS. This is benefical from the fact that both Si3N4 and QDs are discrete trapping centers, suppressing the leakage concern in floating gate memory. Therefore, the tunneling oxide thickness and the read/write bias, respectively, can be scaled down to improve program/erase speed and endurance. The most importance of this work is that the process of Ge QD SONOS hybrid memory is not only simple, but also compatible to the prevailing CMOS technology.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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