本論文利用不同的製程設計功率放大器，在設計上分成兩部份，第一部份為全積體整合矽製程包含CMOS與SiGe設計高效率功率放大器，並使用不同的低損耗阻抗轉換變壓器技術，設計三個高效率E類功率放大器；第二部份則是全積體整合pHEMT製程設計功率放大器以操作於Ka頻帶功率放大器為主要目標。 各電路特性量測如下：傳輸線變壓器技術之CMOS E類功率放大器，增益量測為13.24 dB，1-dB增益壓縮點輸出功率為23.2 dBm，飽和輸出功率為24.7 dBm，效率為33.24 %；雙級傳輸線變壓器技術之CMOS AB類/E類功率放大器，增益量測結果為17.2 dB，1-dB增益壓縮點輸出功率為17.2 dBm，飽和輸出功率為20.03 dBm，效率為17.7 %；巴倫變壓器技術之SiGe E類功率放大器，增益量測結果為11.6 dB，1-dB增益壓縮點輸出功率為20.85 dBm，飽和輸出功率為22.83 dBm，效率為38.41 %；應用於Ka頻段pHEMT製程功率放大器，增益量測結果為15.7 dB，輸入回返損耗約為18.4 dB，輸出回返損耗約為6.1 dB，1-dB增益壓縮點輸出功率為18.7 dBm，飽和輸出功率為19.7 dBm，效率為24.4 %。In this thesis, power amplifiers were designed into both silicon-based and pHEMT technologies. Firstly, fully integrated silicon-based high-efficiency Class-E power amplifiers using SiGe and CMOS processes were designed with low-loss impedance matching transformers technique. Secondly, a fully integrated Ka-band pHEMT power amplifier was implemented. The measured results are summarized as below: the CMOS Class-E power amplifier (PA) using transmission line transformer (TLT) technique achieves a power gain of 13.24 dB, an output power at 1-dB gain compression point (P1dB) of 23.2 dBm, a saturation output power (Psat) of 24.7 dBm and a power-added efficiency (PAE) of 33.24 %. The two-stage CMOS Class-AB/Class-E power amplifier using transmission line transformer technique achieves a power gain of 17.2 dB, a P1dB of 17.2 dBm, a Psat of 20.03 dBm and a PAE of 17.7 %. The SiGe Class-E power amplifier with balun transformer achieves a power gain of 11.16 dB, a P1dB of 20.85 dBm, a Psat of 22.83 dBm and a PAE of 38.41 %. The Ka-band pHEMT power amplifier achieves a power gain of 15.7 dB with input return and output return losses of 18.4 dB and 6.1 dB, a P1dB of 18.7 dBm, a Psat of 19.7 dBm and a PAE of 24.4 %.
