操作於1伏特以下及具固定電壓控制震盪器增益值之鎖相迴路 ; A Sub-1V Phase-Locked Loop with Constant KVCO Technique

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/44742

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题名:	操作於1伏特以下及具固定電壓控制震盪器增益值之鎖相迴路;A Sub-1V Phase-Locked Loop with Constant KVCO Technique
作者:	邱昭彰;Chao-Chang Chiu
贡献者:	電機工程研究所
关键词:	低電壓;low voltage;pll;phase-locked loop
日期:	2010-07-30
上传时间:	2010-12-09 13:54:11 (UTC+8)
出版者:	國立中央大學
摘要:	節能減碳為近年來電路設計上越來越受到重視的議題，鎖相迴路是通訊系統中用來產生同步時脈的重要電路，因此也不能忽略鎖相迴路的功率消耗。降低功率消耗的方法中，最直接的做法就是降低操作電壓；在本論文中提出一個可操作在0.9-V，並輸出1.25-GHz 八個相位的鎖相迴路，以達到高操作頻低功率消耗的目的。但在低電壓的鎖相迴路設計中存在著許多設計上的困難，包括漏電流問題、避免電晶體疊接和過大的臨界電壓值等，如何正確且穩定的操作在低電壓下將在本論文中詳細探討。論文中提出一個具閘級回授充電幫浦，可有效降低充放電之電流不匹配問題，以達到降低壓控震盪器控制電壓之抖動，進而提升鎖相迴路的性能。此外，在寬頻率範圍的多頻帶壓控震盪器設計中，無論是LC震盪器，亦或是環型震盪器往往會存在KVCO (頻率對電壓變化之斜率) 變化劇烈的問題，這將會衍生出許多的問題。因此在本論文亦提出了一個可在製程、電壓、溫度變異下均能避免此問題之全新固定電壓控制震盪器增益值技術。本晶片採用TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V製程實現，當輸出為1.25GHz時，功率消耗為3.7mW，其輸出的抖動為6 ps (p-p)，晶片的核心部分面積為0.09 mm2。The issue of energy saving and carbon reduction is more and more important on circuit design. Phase-locked loop (PLL) is one of the important blocks in communication system. Thus, the power consumption of PLL is not able to ignore. To reduce supply voltage is the easiest way to decrease power consumption. A 0.9-V 1.25 GHz 8-phase PLL is proposed to achieve high output frequency and low power consumption. There are several problems in the low voltage PLL design, inculding leakage current, MOSFET cascade and threshold voltage ,etc. We will discuss about how to operate correctly and stably in low supply voltage. This PLL uses a gate-feedback technique to reduce the current mismatch problem of the charge pump. Therefore, the output frequency jitter will be decreased and the performance of PLL will be improved. In addition, both LC oscillator and ring oscillator have the dramatic variation of KVCO in the wide range multi-band voltage control oscillator design. A novel constant-KVCO technique was proposed to avoid the problem with the process, voltage, and temperature variations. This chip is implemented in TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V process. The output jitter performance of the proposed PLL is 2.79 ps (peak-peak) at 1.25- GHz. The power consumption of the PLL is 3.7 mW at 1.25-GHz and the core area is 0.09 mm2
显示于类别:	[電機工程研究所] 博碩士論文

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