應用於正交分頻多工通訊系統之多載波調變/解調變器與多輸入輸出解碼器之設計與實現; Design and Implementation of Multicarrier Modulator/Demodulator and MIMO Detector for OFDM Communication Systems

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Title:	應用於正交分頻多工通訊系統之多載波調變/解調變器與多輸入輸出解碼器之設計與實現;Design and Implementation of Multicarrier Modulator/Demodulator and MIMO Detector for OFDM Communication Systems
Authors:	饒敬國;Chin-Kuo Jao
Contributors:	電機工程研究所
Keywords:	快速傅立葉轉換;離散哈特萊轉換;正交分頻多工;多輸入多輸出;MIMO;OFDM;DHT;FFT
Date:	2011-06-07
Issue Date:	2012-01-05 14:53:58 (UTC+8)
Abstract:	隨著多媒體應用服務的蓬勃發展以及網際網路與無線通訊的結合，現今的無線通訊系統須具備高傳輸速率的能力以處理日漸增加的資料負載。而高傳輸速率通訊系統所需面對的主要難題是多路徑干擾以及有限的可用傳輸頻寬。為了克服多路徑干擾，調變技術從單載波調變演進到正交分頻多工(OFDM)的多載波調變；為了達到高頻譜效率，天線技術從單輸入單輸出(SISO)的單天線傳輸發展成多輸入多輸出(MIMO)的多天線傳輸。正交分頻多工調變結合多輸入多輸出技術將成為未來通訊系統的發展趨勢。因此本論文分別針對正交分頻多工與多天線技術的關鍵模組–多載波調變/解調變器以及多輸入多輸出解碼器，從演算法到硬體架構層級提出了數個新技術來達到低功耗與高效能的目的。在正交分頻多工的傳收機設計中，傳統上都是利用快速傅立葉轉換(FFT)處理器做為多載波訊號解調器。由於快速傅立葉轉換的演算法研究發展已發展地相當成熟，欲從演算法層級來減低運算複雜度已經遇到了瓶頸，因此本論文提出利用實數運算的離散哈特萊轉換(discrete Hartley transform, DHT)來取代複數離散傅立葉轉換(DFT)的構想。然而離散哈特萊轉換的正交分頻多工系統並不像離散傅立葉轉換擁有環狀捲積(circular convolution)特性，因此造成在多路徑衰減通道產生子載波相互耦合(intercarrier coupling, ICC)的問題。為了解決此問題，我們利用離散哈特萊轉換矩陣的互補對(complementary pair)特性設計了可使通道矩陣對角化的DHT-based OFDM架構。此外，為了增加頻寬傳輸效率，所提出的DHT-based多載波調變/解調變器採用了兩個實數快速哈特萊轉換(FHT)核心和一個後處理單元(PPU)，如此即可適用於二維的QAM調變方法。為了驗證此構想的優點，我們將此DHT-based多載波調變/解調變器應用於IEEE 802.11a/g無線區域網路系統中。在硬體設計考量上，藉由所提出的平行式DCT-based FHT演算法與記憶體架構，可有效減少運算複雜度與記憶體存取次數以降低功率消耗。本電路的訊號量化雜訊比(SQNR)超過44 dB，在接收機訊雜比為26 dB時(64-QAM, 3/4碼率)，此電路的施行損失(implementation loss)可小於0.1 dB。我們將所提出之DHT-based調變/解調變器使用台積電0.18-μm CMOS製程實現，其核心面積為928×935 μm2。此晶片最高操作頻率為54 MHz，可支援兩路的多輸入輸出正交分頻多工訊號。當工作在20 MHz頻率與1.8伏特時，其功率消耗為20.16 mW。在多輸入多輸出解碼器的設計中，本論文提出了一個可支援2×2、4×4、8×8天線組態以及QPSK、16-QAM、64-QAM調變模式的高速低功率解碼器。藉由所提出的結合離散K最佳(distributed K-best, DKB)與連續干擾消除(successive interference cancellation, SIC)演算法，可大幅降低搜尋複雜度。與傳統K最佳演算法相比，離散K最佳演算法在每層所需拜訪的節點數可以從K√M減少到2K-1 (K為候選節點數，M為信號星座點大小)。為了讓此多輸入輸出解碼器能支援多種天線組態，我們將DKB與SIC方法設計成一些基本方塊，透過這些基本方塊可以彈性的將解碼器組裝成不同天線組態的電路。在硬體設計考量上，此設計能夠避免傳統K最佳演算法需要複雜的排序電路，此外我們也提出新的位移乘法器(shift multiplier, SM)來取代PED運算過程中所需的傳統乘法器，可以節省20%的功率消耗。我們將此多輸入輸出解碼器用聯電90-nm CMOS製程實現，所完成之高速低功率解碼器其核心面積為880×880μm2，可支援2×2、4×4、8×8天線組態以及QPSK、16-QAM、64-QAM調變模式。在8×8、64-QAM、K=5的傳輸模式，此晶片操作在101 MHz頻率與1.0伏特下可達到970 Mbps的解碼速率，並且僅需功率消耗12 mW。 Due to the well development of multimedia service and the convergence of wireless with the Internet, the modern communication systems should have the ability of high throughput rate to deal with the increasing data loading. The main challenges for a high throughput communication system are multipath interference and limited channel bandwidth. In order to overcome multipath interference, the digital modulation scheme advances from single carrier modulation to multicarrier modulation, i.e., orthogonal frequency-division multiplexing (OFDM); the antenna technique also progresses from single-antenna (single-input single-output, SISO) system to multiple-antenna (multiple-input multiple-output, MIMO) system for the enhancement of spectrum efficiency. As a result, OFDM modulation combining with MIMO techniques will be the evolutional trend for the next generation communication system. In this dissertation, the key components of OFDM and multiple-antenna techniques, multicarrier modulator/demodulator and MIMO detector, are designed and implemented from algorithm to hardware architecture level to achieve the low-power and high-performance targets. The conventional OFDM transceiver usually uses FFT processor as the multicarrier demodulator. However, the study of FFT algorithm has been developed maturely. It has becomegoes to a bottleneck for FFT to reduce the computational complexity from algorithm level. Hence, we propose an idea to substitute DFT by DHT in an OFDM system. Nevertheless, unlike the DFT-OFDM system, the DHT-based OFDM system does not have the circular convolution property, which would cause the intercarrier coupling (ICC) problem in a multipath fading channel. In order to solve this problem, we use the complementary property of DHT matrix to devise a DHT-based OFDM architecture that can perfectly diagonalize the channel matrix. Besides, the proposed DHT-based multicarrier modulator/demodulator employs two real-valued fast DHT (FHT) kernels and one processing unit. It can be applied to the two-dimensional modulation scheme, such as QAM. In order to verify the advantages of this idea, we have demonstrated the DHT-based multicarrier modulator/demodulator for IEEE 802.11a/g application. From the hardware design aspects, with the proposed parallel DCT-based FHT algorithm and memory-based architecture, the computational complexity and memory accesses can be effectively reduced. The signal-to-quantization ratio (SQNR) of this circuit is more thanover 44 dB. When the receiver SNR is 26 dB (64-QAM, 3/4 coding rate), the implementation loss of this circuit will be smaller than 0.1 dB. A test chip of the proposed DHT-based modulator/demodulator has been fabricated in a 0.18-μm CMOS technology with a core area of 928×935 μm2. The maximum operation frequency of this chip is 54 MHz, which can support two data streams for MIMO-OFDM. The average power consumption is about 20.16 mW at 20 MHz and 1.8 V supply voltage. In the MIMO detector design, a high-throughput and low-power MIMO detector which can support 2×2, 4×4, 8×8 antenna configurations and QPSK, 16-QAM, 64-QAM modulation schemes has been proposed. The detection complexity is reduced considerably by using the combined distributed K-best (DKB) and successive interference cancellation (SIC) algorithm. Compared with the conventional K-best algorithm, the DKB algorithm reduces the number of visited nodes at each layer from K√Mto 2K-1 (K is the candidate number and M is the constellation size). The DKB and SIC schemes are designed as several elementary blocks for the antenna scalable ability. Then the antenna scalable architecture can be flexibly constructed by these elementary building blocks. In the hardware design consideration, our design avoids the complicated sorting circuit that is required in the conventional K-best detector. In addition, the conventional multipliers used for PED calculation are replaced by the proposed shift multiplier (SM) technique. It can save about 20% power consumption. A test chip of the proposed configurable MIMO detector has been fabricated in a 90-nm CMOS technology with a core area of 880×880 μm2. In the 8×8, 64-QAM, K=5 transmission mode, the power dissipation is merely 12 mW at 101 MHz clock rate and 1.0 V supply voltage, and the decoding throughput of this chip is up to 970 Mbps.
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