具可適性自動調節機制之低複雜度K-最佳多輸入輸出解碼器; A Low-complexity K-Best Detector with Adaptive Self-adjusting Mechanisms

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Title:	具可適性自動調節機制之低複雜度K-最佳多輸入輸出解碼器;A Low-complexity K-Best Detector with Adaptive Self-adjusting Mechanisms
Authors:	鄭凱中;Kai-chung Cheng
Contributors:	電機工程研究所
Keywords:	多輸入輸出系統;適應性連續消除;適應性K值;分佈型K最佳;adaptive K value;adaptive SIC;MIMO system;distributed K best
Date:	2011-07-26
Issue Date:	2012-01-05 14:56:29 (UTC+8)
Abstract:	本論文提出一以傳統分佈型K-最佳演算法為基礎的低複雜度K-最佳多輸入輸出解碼器，本解碼器結合了兩種可適性自動調節機制來達到比傳統分佈型K-最佳演算法還低的運算複雜度，分別為適應性連續消除機制與適應性K值選取機制。適應性連續消除機制的原理為於每一層解碼訊號時計算每個母點的中心點，運用這些中心點的相同性來判斷是否執行連續消除演算法。然而適應性K值選取機制的原理不同於傳統適應性K值選取機制需要估測SNR大小來調整K值大小，所提出之機制僅需使用每一層中最小與次小的PED來決定K值大小，並且提出一套關於K值選取的設計流程，使適應性K值選取機制能更有效率得被使用。與傳統分佈型K-最佳演算法作比較，所提出之演算法因加入這兩種可適性機制後能在錯誤率不提高為前提下擁有更低的運算複雜度，並且設計適當的電路架構使其能更有效率的降低功率消耗。最後本論文使用SMIMS VeriEnterprise Xilinx FPGA板驗證其電路功能，並且以TSMC-90nm製程實現所提出之解碼器。該晶片核心面積為0.740 mm x 0.738 mm，當晶片操作於125MHz以及1V的工作電壓下其功率消耗為22mW，並且訊號最大吞吐量可達124Mbps。 The thesis proposed a low complexity K-best MIMO detector based onconventional distributed K-best(DKB).The proposed algorithm combines two self-adjusting mechanisms which are adaptive successive interference cancellation (ADSIC) and adaptive K value chooser (ADK). The principle of ADSIC is to determine the execution of SIC based on the similarity of center-points. The center-points can be found first by calculating every root’s signal in each layer, then identify the one that has the least partial Euclidian distance (PED). After contrasting the one with each other, make a decision to execute SIC by the statistic of the same cases. The goal of the other mechanism is that ADK choose an appropriate K value at each layer by non-SNR measurement. The purpose is to put forward a design flow by selecting the appropriate threshold value and estimating the order of noise by the smallest PED and the second smaller PED. The proposed algorithm has lower computational complexity comparing with conventional DKB due to smaller BER loss; in addition, lower power consumption is achieved by utilizing architecture with gated clock. In order to verify the function of the algorithm, a chip is implemented using TSMC 90nm Technology and SMIMS VeriEnterprise Xilinx FPGA verification board. The functionality of the chip is validated with core size of 0.740 mm x 0.738 mm, clock frequency of 125MHz, power consumption of 22mW and maximum throughput of 124Mbps.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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