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    題名: A 0.5-V 0.42.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip
    作者: Cheng,KH;Tsai,YC;Lo,YL;Huang,JS
    貢獻者: 電機工程學系
    關鍵詞: CMOS CIRCUIT TECHNIQUE;LOW-VOLTAGE;PLL;GENERATION;BANDWIDTH;DESIGN;POWER;DLL
    日期: 2011
    上傳時間: 2012-03-28 10:13:14 (UTC+8)
    出版者: 國立中央大學
    摘要: A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (K(VCO)), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular V(T) (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is -87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW(excluding the buffers). The core area is 0.074 mm(2).
    關聯: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
    顯示於類別:[電機工程學系] 期刊論文

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