紫外光輔助準晶矽薄膜在多孔層上之製作與研究;The study of the quasi-crystal silicon thin film with UV assisted in the porous silicon layer.

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Title:	紫外光輔助準晶矽薄膜在多孔層上之製作與研究;The study of the quasi-crystal silicon thin film with UV assisted in the porous silicon layer.
Authors:	宋炳儒;Song,Bing-ru
Contributors:	機械工程研究所
Keywords:	多孔矽;準晶系;薄膜;紫外光;UV;thin film;porous silicon;quasi-crystalline
Date:	2012-07-06
Issue Date:	2012-09-11 18:16:34 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著時代的發展，半導體製程技術依循著摩耳定律（Moore，s Law）發展，目前進入奈米製程，開始28奈米和22奈米節點之量產。絕緣層矽晶（Silicon on insulator, SOI）材料結構具備可以解決於傳統矽塊材（Bulk Silicon）晶圓材料上製作尺寸越來越小之元件所帶來的諸多問題，如：寄生效應、閉鎖效應、軟錯效應、基材漏電流與過熱等問題。Smart-CutR製程為近來最常用之技術，利用高劑量氫離子佈植於矽晶圓內，再經晶圓鍵合製程與高溫退火處理，使氫離子聚集產生剝離以達到薄膜轉移之目的。但離子佈植機設備高昂，且高強度離子束易損傷晶圓，佈植深度難以超過一微米，故改以利用紫外光輔助電化學蝕刻的方式製作出厚層的薄膜轉移材料。本實驗研究之目的為使用紫外光輔助電化學蝕刻的方式，依照不同蝕刻參數，蝕刻P型重掺雜矽晶圓，蝕刻出雙層多孔矽結構，再利用Argon高溫退火處理，製作出具深埋破裂層與微米厚的多孔回復晶矽薄膜，其薄膜為準晶矽結構。The semiconductor manufacturing technology follows the Moor’s law in the past. The development of the semiconductor industry has entered the nanoscale process, such as the 28 nm and the 22 nm. Silicon on insulator, SOI, which has the material structure can solve the problem of the devices been manufactured to be smaller with the traditional bulk silicon wafer, such as the parasitic capacitance, the latch-up, short channel effects, the substrate leakage current and overheating, and so on. Smart-CutR process is a common technology for manufacturing the SOI material. By implanting the high doses of hydrogen ion into the silicon wafer, wafer bonding process and annealing process, the hydrogen ions will accumulate and thus create cracks to finish thin film transfer. The ions implantation equipment is easy to cause damage because of high ion implanting doses into silicon wafer, and which is expensive. It’s difficult to obtain over 1 micron of implanting depth. Thus, the UV-assisted electrochemical etching method can achieve thicker film transfer and the price is cheaper.The purpose of this study is to use the UV-assisted electrochemical etching method, heavily doped P-type silicon wafer was electrochemically etched based on different etching parameters which forms a porous silicon (PS) bilayer. Then the PS wafer was annealed at the high temperature to manufacture the PS bilayer with a buried separation and recrystallization layer with a few micros thickness, which was the structure of the quasi-crystalline silicon.
Appears in Collections:	[Graduate Institute of Mechanical Engineering] Electronic Thesis & Dissertation

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