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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/74980


    Title: 超薄層異質通道場效電晶體及單石三維靜態隨機存取記憶體考慮負交疊設計之研究;Analysis of Ultra-Thin-Body Hetero-channel MOSFETs and Monolithic 3D SRAM Cells Considering the Impact of Underlap Design
    Authors: 黃子承;Huang, Zie-Cheng
    Contributors: 電機工程學系
    Keywords: 超薄層異質通道場效電晶體及單石三維靜態隨機存取記憶體
    Date: 2017-08-22
    Issue Date: 2017-10-27 16:14:44 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 摘要
    隨著製程技術的演進,高功率消耗(Power consumption)對於半導體元件及其電路是一極大的考驗,靜態隨機存取記憶體(Satatic Random Access Memory, SRAM)佔據晶片上主要的面積。因此,降低SRAM之功率消耗極為重要,降低操作電壓為一有效方式,可降低動態及靜態功率消耗。然而,對於低電壓的操作環境,會造成SRAM的穩定度(Static Noise Margin, SNM)有顯著的降低。因此,本論文研究單石三維(Monolithic 3D)異質通道SRAM的特性,並利用負交疊(Underlap)設計來改善讀取及寫入的穩定度,論文內容分為兩個主題,第一部分為分析超薄層InGaAs金氧半場效電晶體(Ultra-Thin-Body InGaAs-OI MOSFET),考慮對稱與非對稱的閘極至源極/汲極的負交疊(Symmetric and Asymmetric Gate to Source/Drain Underlap)的設計,以及不同的側壁空間層(Spacer)材料,並分析改變閘極功函數(Work Function, WF)對導通電流所產生的影響,研究結果顯示透過低介電常數的Spacer材料,和非對稱的負交疊設計,可使超薄層InGaAs金氧半場效電晶體之切換速度(Switching Time, ST)大幅改善。
    論文的第二部分為分析三五族異質接面(InGaAs-OI/GeOI MOSFETs)靜態隨機存取記憶體,同時考慮單石三維及負交疊設計,利單石三維設計縮小SRAM單元之面積,並改善其穩定度,然後,為了提升讀取穩定度,我們需要弱化SRAM裡的Access電晶體,而為了提升寫入穩定度,我們需要強化Access電晶體,因此,SRAM的設計裡存在著同時改善讀取及寫入穩定度的矛盾,而利用負交疊設計,即可用來避免同時提升讀取及寫入穩定度的矛盾,使在不影響寫入穩定度的情況下,大幅改善靜態隨機存取記憶體之讀取穩定度,與傳統的靜態隨機存取記憶體單元相比,我們提出並分析三種考慮負交疊設計的靜態隨機存取記憶體單元,並考慮不同的單石三維(Monolithic 3D)堆疊設計與不同的Spacer材料,研究結果顯示,使用低介電常數的Spacer材料,並考慮Pull-down元件疊在Pull-up元件之上(PD/PU)的單石三維設計,以及在Access電晶體及Pull-up電晶體上使用負交疊設計,使讀取穩定度可有38%的提升。
    ;Abstract
    Power consumption is a major challenge for semiconductor devices scaling. Lowering supply voltage is an efficient method for reducing the static and dynamic power. However, lowering supply voltage also degrades the static noise margin of SRAM cells. In this thesis, we analyze the monolithic 3D hetero-channel SRAM cells with underlap design to improve its stability and mitigate the conflict between read and write stability. First, we analyze the performance of Ultra-thin-body (UTB) InGaAs-OI MOSFETs considering the symmetry and asymmetry gate-to-source/drain underlap design and different spacer materials. The impact of metal gate work function on the drive current and switching time of UTB InGaAs-OI MOSFETs is also investigated. The results show that UTB InGaAs-OI MOSFET with low-k spacer and asymmetry underlap design exhibits lower switching time. Second, we analyze the stability and performance of monolithic 3D hetero-channel SRAM cells (InGaAs-OI for NFET, GeOI for PFET) with underlap design. Three kinds of SRAM cells with different underlap design are also investigated. Results show that for monolithic 3D SRAM cell with vacuum spacer using two-tier design (upper-tier is pull-down NFET, and bottom-tier is pull-up PFET), and both access and pull-up transistors using asymmetry underlap design can increase the read static noise margin by 38%.
    Appears in Collections:[電機工程研究所] 博碩士論文

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