| 摘要: | 隨著積體電路製造技術促進高速數據傳輸的發展，資料傳輸量發展至每秒數兆位元(Gbps)。高速串列連結技術(High-Speed Serial Link Technology)是現今主要數據傳輸技術，亦被廣泛應用在有線收發裝置上，可以分為四個主要部分：發射端(TX)、接收端(RX)、傳輸通道(Channel)和時脈電路(CLK)。
發射端主要的功能為編碼，以確保資料的1和0的數量一致，並具有將資料串列化和功能模組化的用途。當資料傳輸速率已達每秒數兆位元，發射端的傳輸資料往往伴隨高次諧波，這將導致電磁干擾(Electromagnetic Interference, EMI)，並且嚴重影響周遭其他裝置。接收端主要的功能是等化，以確保接收到的資料和送出的資料一致，並具有將資料並列化和功能模組化的用途。隨著傳輸速率上升，訊號在傳輸通道中的損失越來越嚴重，加上傳輸通道的變異性，單一的補償機制已不敷使用，因此訊號完整性(Signal Integrity, SI)的考量也更顯得重要。晶片內外的雜訊來源，也是高速串列連結設計挑戰之一，包括有抖動，信號間的歪斜、電源和基體雜訊、其他線路產生的串擾以及設備本身的雜訊。因此，時脈電路也是必須要考慮周到的功能區塊。除此之外，為了使其具備更廣泛的應用性，拓展時脈電路的功能是一個重要議題。
於本論文中，對於發射端、接收端、傳輸通道和時脈電路的關鍵技術進行了討論和分析，並提出了相對應的電路以滿足其需求。透過提出具電磁干擾抑制技術之展頻時脈產生器(Spread-Spectrum Clock Generator, SSCG)及電源管理電路(Power Management In-tegrated Circuit, PMIC)，可降低電磁干擾帶來的影響。開發出具訊號完整性強化能力之連續時間線性等化器(Continuous Time Linear Equalizer, CTLE)和資料與時脈回復電路(Clock and Data Recovery, CDR)，可進一步提升接收端訊號的等化能力和可靠性。希望藉由抑制電磁干擾和訊號完整性強化技術，開發出適用於次世代的高速串列收發器，期盼其可具有低電磁干擾、高速資料傳輸功能及良好功率等效率表現。時脈電路中最常被採用的架構為鎖相迴路(Phase-Locked Loop, PLL)和延遲鎖定迴路(Delay-Lock Loop, DLL)，針對四個關鍵特性，分別是寬範圍(Wide-Range)技術、快速鎖定(Fast-Locking)技術、次諧波注入鎖定(Sub-Harmonically Injection-Locked)技術和非石英振盪器(Crystal-Less Clock Generator, CLCG)進行功能強化，希望透過這些技術使得時脈電路的功能可以更適用於高速的串列連結介面中。
;Advance in integrated circuit fabrication technology facilitates the high-speed transmission of data to be upward evolved into several gigabits per second (Gbps). The high-speed serial link (HSSL) technology is the major technique in modern data transmission. It is widely employed in wireline SerDes applications. The architecture of HSSL can be divided into four major parts, Transmitter (TX), Receiver (RX), Channel and Clock (CLK).
The main work of the TX is the coding, to ensure that 1 and 0 are the same, in addition to the serialization and the modular. As the transmitted data rate has been upgraded into milti-Gbps, the signal of the data launched by the TX accompanies the higher order harmonics. It results in the power-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipment in the vicinity. The main work of the RX is the equalization, to ensure that the received data is the same as transmitted data, in addition to the deserialization and the modular. The higher data transmission has the more channel loss. Furthermore, a simple compensation mechanism is not suitable for various transmission channels. Therefore, the signal integrity (SI) has to been considered carefully. On-chip and off-chip noise sources are also a challenge for the HSSL. They include the jitter, the inter-signal skew, the power supply and substrate noises, the crosstalk generated by other lines and the noise of the device itself. Therefore, the CLK is also the part have to be considerate well. Moreover, expanding the functionality of the clock circuit is an important issue to make it more widely applicable.
In this dissertation, the key techniques of the four major parts, TX, RX, Channel and CLK, in HSSL are discussed and analyzed and corresponding circuit designs are presented to meet their needs, respectively. Through the introduction of a spread-spectrum clock generator and a power management integrated circuit with EMI suppression technology, the effects of EMI can be reduced. Through the introduction of a continuous time linear equalizer and a clock and data recovery with SI enhancement technology, the equalization ability and reliability of the signal on the RX side can further be improved. By the EMIsuppression and the SI enhancement technologies, the capabilities of low-EMI, high-speed data transmission and good power-efficient are derived for the next generation HSSL. The most common architectures of the clock generator are the phase-locked loop and delay-locked loop. To extend the functions of the four key features, which are the wide-range technique, the fast-locking technique, the sub-harmonically injection-locked technique and the crystal-less clock generator, it is expected that the functions of the clock generator can be more suitable for applications requiring an interface of the HSSL system. |
