| 摘要: | 本論文主要為設計研製收發機前端之低雜訊放大器及功率放大器，包含兩個分別操作於C/Ku頻帶的低雜訊放大器及兩個操作於Ka頻帶的功率放大器。第二章首先使用台積電 0.18 μm CMOS製程設計三級疊接低雜訊放大器，小訊號增益達到22.4 dB，3 dB頻寬從11至19 GHz，頻率在15 GHz時有最小雜訊指數4 dB，晶片面積為0.84 x 0.8 mm2。進一步將疊接架構修改為共源極，以減少低雜訊放大器之直流功率消耗。電路使用穩懋 0.15 μm GaAs製程實現，包括三級共源極增益級，小訊號增益達到28 dB，3 dB頻寬從4至16 GHz，頻率在10 GHz時有最小雜訊指數2 dB，晶片面積為2 x 1 mm2。
第三章使用穩懋 0.1 μm GaAs製程設計一個Ka頻帶雙功率合併功率放大器，使用雙合併技術來提升輸出功率，第一級增益單元串聯一組電阻-電容並聯來改善穩定度，第二級則兩兩電晶體合併，共合併四顆電晶體。另介紹放大器穩定度檢查電路，除了檢查放大器整體電路的穩定係數K值，檢查多級放大器穩定度時作級間穩定度模擬，以及檢查大功率電路穩定度的非線性穩定度模擬，以及加入奇模抑制電阻後進行的奇模穩定度模擬。其量測得小訊號增10 dB，3 dB頻寬為從33至43 GHz，輸入1 dB增益壓縮點(IP1dB)約為16 dBm，而輸出1 dB增益壓縮點(OP1dB)約為24.6 dBm，飽和功率(Psat) 為26 dBm，功率消耗為2084 mW，晶片面積為2 x 1 mm2。
在第四章使用台積電 90 nm CMOS製程設計層疊式功率放大器。同樣使用雙合併技術來作功率整合，而為了在取得足夠輸出功率時，也能有足夠的增益頻寬表現，使用T型匹配於功率放大器的匹配網路。第一級增益單元使用層疊式以增加電路增益，第二級則兩兩並聯層疊式合併作為功率元以取得較高的輸出功率。其量測得小訊號增益10.3 dB，3 dB頻寬為從30至48 GHz，輸入1 dB增益壓縮點(IP1dB)約為5 dBm，而輸出1 dB增益壓縮點(OP1dB)約為14 dBm，飽和功率(Psat) 為16 dBm，功率消耗為765 mW。且可藉由提升汲極偏壓到2.8V，於30至39 GHz頻率範圍得到大於16 dBm的飽和功率，且於31 GHz得到最高19 dBm的飽和功率，晶片面積為 0.88 x 0.84 mm2。
最後，於第五章呈現被動式二極體混波器以及接收器前端電路的設計。本設計是使用穩懋增強-空乏模態( ED Mode ) 0.15 μm GaAs製程。二極體混波器的有效操作頻帶範圍是從25 GHz到50 GHz，並且訂定38 GHz為電路中心頻率。在10 dBm的本地振盪驅動源的情況下，表現出的轉換增益約為-6 dB，晶片面積為1 x 1 mm2。而二極體混波器受益於本身被動的設計，直流功耗甚小。後整合穩懋0.15 μm GaAs製程的Ka頻帶低雜訊放大器，最後實現一個Ka頻帶接收器前端電路，擁有27-37 GHz的RF操作頻率，轉換增益最高為31 dB，雜訊指數2 dB，輸入1 dB增益壓縮點為-6 dBm，晶片面積為3 x 1.5 mm2。
;In this thesis, design of several C/Ku bands low noise amplifiers (LNAs) and power amplifiers (PAs) are presentd. A Ku-band three-stage cascode LNA using TSMC 0.18 μm CMOS process is presented in Chapter 2. The cascode CMOS LNA exhibits a 22.4-dB gain, 3-dB bandwidth from 11 to 19 GHz, a minimum noise figure of 4 dB at 15 GHz. The chip size of the three-stage LNA is 0.84 x 0.8 mm2. A broadband LNA is designed using common-source (CS) topology to reduce dc power consumption, and the circuit is fabricated in 0.15 μm GaAs process provided by WIN Semiconductors Corporation. The three-stage GaAs LNA exhibits a 28-dB gain, 3-dB bandwidth from 4 to 16 GHz, a minimum noise figure of 2 dB at 10 GHz. The chip size of the three-stage LNA is 2 x 1 mm2.
In Chapter 3, a Ka-band binary-combined power amplifier using WIN 0.1 μm GaAs procss is presented. The first stage uses a resistor-capacitor network to improve stability. The second stage combines 4 FETs with a total gate periphery of 800 μm. The stability analysis is summarized, including K factor, interstage stability, non-linear stability, and odd mode stability after adding the odd-mode suppression resistors . The PA exhibits a 10-dB gain, 3 dB bandwidth from 30 to 43 GHz , an output 1-dB compression point of 24.6 dBm, and a saturation output power of 26-dBm. The chip size of the PA is 2 x 1 mm2.
A CMOS stacked PA is presented in Chapter 4. The first stage uses a stacked structure as the gain unit to increase the gain performance, and the second stage combines two power units of stacked structure in parallel to achieve higher output power. In order to further improve the broadband gain frequency response with high output power, the T-model matching network is employed in the matching network of the PA. The stacked PA exhibits 10.3-dB gain, 3-dB bandwidth from 30 to 48 GHz, an output 1-dB compression point of 14 dBm, and a saturation output power of 16-dBm. The DC power comsumption is 765 mW. The chip size of the PA is 0.88 x 0.84 mm2.
Finally, design of the Ka-band GaAs diode mixer is presentd, the mixer has 3 dB bandwidth between 25 GHz and 50 GHz with a center frequency of 38 GHz. The diode mixer shows up to a conversion gain of -6-dB with a 10-dBm local oscillation (LO) driving power, without DC power consumption. The chip size of the mixer is 1 x 1 mm2. The mixer is further integrated with a 4-stage LNA to lower noise figure for some Ka-band receiving applications. The integrated front-end circuit shows a 31-dB conversion gain with a 10 dBm LO driving power, 2-dB noise figure and an output 1 dB gain compression point is -6 dBm. The chip size of the front- end circuit is 3 x 1.5 mm2. |
