English  |  正體中文  |  简体中文  |  Items with full text/Total items : 78852/78852 (100%)
Visitors : 36426833      Online Users : 757
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/84257

    Title: 使用傳輸線基全通網路之Ka頻段被動式相位偏移器;Ka-Band Passive Phase Shifters Using Transmission-Line-Based All-Pass Networks
    Authors: 洪維鴻;Hong, Wei-Hong
    Contributors: 電機工程學系
    Keywords: 相位偏移器
    Date: 2020-08-24
    Issue Date: 2020-09-02 18:34:08 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 相位陣列常用於雷達系統中,而相位偏移器在相位陣列中是關鍵的電路元件之一。相位偏移器功能為提供各天線可調的相移量,用於調整波束的方向來達到波束掃描的效果。另外,在第五代行動通訊系統中,相位陣列也扮演重要的角色。在本論文中,我們採用傳輸線基全通網路架構,並使用TSMC 0.18-μm CMOS製程實現操作於35 GHz的四位元與五位元被動式相位偏移器。
    在第二章中,我們採用傳輸線基全通網路架構,設計四位元被動式相移器。系統阻抗定為25 Ω,全通網路中傳輸線的特徵阻抗使用50 Ω。其中,22.5°、45°及90°相移級皆採用一級的傳輸線基全通網路架構,180°相移級則採用兩級中心頻率錯開的傳輸線基全通網路串接而成,以增加相位偏移量平坦的頻寬;相移器所佔的晶片面積為0.75×0.75 mm2。模擬結果顯示,在33.2 GHz 至40.8 GHz(20.5% 頻寬),均方根相位誤差小於3°,振幅誤差在 ±1 dB內,植入損耗低於16.9 dB。量測結果顯示,所有狀態的相移量皆有變小,造成均方根相位誤差變大甚多。均方根相位誤差最小值19.2°,發生在42.1 GHz;在Ka頻段內植入損耗僅低於24.4 dB。經重新模擬,我們發現若減少電路中MIM電容的電容值與電晶體的寄生電容值,將會使模擬結果與量測結果較為貼合。
    在第三章中,我們採用相同的傳輸線基全通網路架構設計一個五位元相位偏移器;設計流程與前章相同,差異在於使用系統阻抗定為50 Ω及傳輸線特徵阻抗使用70.7 Ω。模擬結果顯示,在31.8 GHz 至41.7 GHz(26.9% 頻寬),均方根相位誤差小於3°,振幅誤差在 ±1 dB內,植入損耗低於18.9 dB。量測結果顯示,與第二章的四位元相移器相同,此相移器所有狀態的相移量皆有變小,造成均方根相位誤差變大甚多。均方根相位誤差最小值27.9°,發生在38.5 GHz;在Ka頻段內植入損耗僅低於26.6 dB。
    ;Phased arrays are often used in radars. Phase shifters are essential components in a phased array, where the function of a phase shifter is to provide adjustable phase shift to individual antenna elements, thus steering the beam direction for scanning purpose. Besides, in fifth-generation mobile communication, phased arrays also play important roles. In this thesis, 35-GHz 4-bit and 5-bit passive phase shifters are designed by adopting transmission-line-based all-pass network topology and implemented using TSMC 0.18-μm CMOS process.
    In Chapter 2, a 4-bit passive phase shifter is designed using transmission-line-based all-pass network. The system impedance is set to be 25 Ω, whereas the characteristic impedance of the transmission lines used in the networks is chosen to be 50 Ω. In the phase shifter, the 22.5°, 45°, and 90° phase-shifting stages all use single-stage transmission-line-based all-pass network, whereas 180° phase-shifting stage is realized by cascading two stages of transmission-line-based all-pass networks with staggered center frequencies for wider phase-shift bandwidth. The phase shifter occupies a chip area of 0.75×0.75 mm2. Simulation results show that, between 33.2 GHz and 40.8 GHz (20.5% bandwidth), the RMS phase error is less than 3°, the amplitude error is within ±1 dB, and the insertion loss is less than 16.9 dB. However, measurement results show that, for all 16 states, the phase shifts are smaller than expected, causing the RMS phase error to increase a lot. The measured RMS phase error exhibits a minimum of 19.2° at 42.1 GHz. The insertion loss is only less than 24.4 dB within Ka band. After re-simulation, it is found that, if the capacitances of the MIM capacitors and parasitic capacitances of the MOSFETs are reduced, the simulation results would fit better to the measurement results.
    In Chapter 3, a 5-bit phase shifter is designed by adopting the same transmission-line-based all-pass network topology with the same design procedure, except that the system impedance and the transmission-line characteristic impedance are chosen to be 50 Ω and 70.7 Ω, respectively. Simulation results show that, between 31.8 GHz and 41.7 GHz (26.9% bandwidth), the RMS phase error is less than 3°, the amplitude error is within ±1 dB, and the insertion loss is less than 18.9 dB. However, same as the phase shifter describe in Chapter 2, measurement results of this phase shifter show that the phase shifts for all states all become smaller than expected and the RMS phase error increases a lot. The measured RMS phase error exhibits a minimum of 27.9° at 38.5 GHz. The insertion loss is only less than 26.6 dB within Ka band.
    In this thesis, passive digital phase shifters are successfully designed using transmission-line-based all-pass network. However, large discrepancies between the measured and simulated results are observed. Nevertheless, after re-simulations, part of the possible reasons for the large discrepancy has been proposed.
    Appears in Collections:[電機工程研究所] 博碩士論文

    Files in This Item:

    File Description SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明