應用 CMOS 製程之 Q 頻段低雜訊放大 器與寬頻混波器暨 W 頻段降頻器研製;Design of Q-Band Low-Noise Amplifier, Wideband Mixer, and W-Band Downconverter Using CMOS Process.

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Title:	應用 CMOS 製程之 Q 頻段低雜訊放大器與寬頻混波器暨 W 頻段降頻器研製;Design of Q-Band Low-Noise Amplifier, Wideband Mixer, and W-Band Downconverter Using CMOS Process.
Authors:	黃柔尹;Huang, Rou-Yin
Contributors:	電機工程學系
Keywords:	低雜訊放大器;混波器;LNA;Mixer
Date:	2023-08-15
Issue Date:	2024-09-19 17:03:36 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文研究目標為應用CMOS製程設計Q頻段低雜訊放大器、寬頻混波器以及W頻段低雜訊放大器與降頻器。第二章提出使用台積電0.18 μm CMOS製程設計操作於Q頻段低雜訊放大器，作為降頻器之前端放大器，為達到低雜訊與高增益特性，採用五級架構實現。此電路可達到16.4 dB之最大增益與7.3 dB之最小雜訊指數，頻寬為35.7至41.7 GHz，電路線性度之1 dB增益壓縮點輸出功率為3 dBm與-3 dBm的三階交調輸入功率，電路總功耗為73 mW，總晶片面積為0.8 × 0.7 mm2。第三章提出使用台積電0.18 μm CMOS製程操作於Q頻段混波器，採用達靈頓混頻單元與本地振盪源閘極饋入之電路架構，對於不同的混頻核心電路架構與電晶體尺寸進行分析，達到最佳轉換增益。並於降頻器之輸入端設計馬相平衡不平衡轉換器，針對耦合線長度差以及補償線長度分析，提升本地振盪埠至射頻埠之隔離度。當降頻器給定本地振盪功率為5 dBm時轉換增益為-15 dB，射頻埠頻寬為35至45 GHz，本地振盪埠之射頻埠隔離度在30 GHz為38 dB，1 dB增益壓縮點輸入功率為2 dBm，電路功耗為1 mW，整體晶片面積為0.88×0.77 mm2。第四章提出使用台積電90 nm CMOS製程設計之W頻段降頻器。首先設計位於電路前端的W頻段低雜訊放大器，但在W頻段時單顆電晶體能提供之增益僅有2 dB，而疊接架構雜訊指數過大，故採用六級共源極架構增加電路增益並降低雜訊指數。此電路可達到13 dB之最大增益與8 dB之最小雜訊指數，且電路總功耗僅為10 mW，低雜訊放大器晶片面積為0.73 × 0.81 mm2。接著，將低雜訊放大器與混波器整合為低雜訊W頻段降頻器，將轉換增益提升至3.3 dB，並降低最小雜訊指數至11 dB以及提高本地振盪埠至射頻埠隔離度，電路總功耗僅有15 mW，整體晶片面積為1.4×0.84 mm2。 ;In this thesis, a Q-band low-noise amplifiers (LNAs), wideband mixers, and W-band LNA with downconverters using CMOS process technology. In Chapter 2, a Q-band LNA using TSMC 0.18 μm CMOS process is presented as a pre-amplifier for radiometer receiver to achieve low noise and high gain characteristics, a five-stage architecture is used. The measured small signal gain is 16.4 dB with 3-dB bandwidth from 35.7 to 41.7 GHz, and minimum noise figure of 7.3 dB at 39 GHz. An output 1-dB compression power of 3 dBm and an IIP3 of -3 dBm. The total dc power consumption of 73 mW. The chip size of the LNA is 0.8 × 0.7 mm2. In Chapter 3, a Q-band mixer is realized TSMC 0.18 μm CMOS process. The circuit adopts a Darlington mixing cell with LO source-pumped architecture to achieve optimal conversion gain. Different mixer core circuit architectures and transistor sizes are analyzed for performance optimization. a Marchand Balun is designed at the input of the RF port to enhance isolation from LO port to RF port, the length of the compensated line and couple line in Marchand Balun are further analyzed and discussed in this chapter. While the LO power is 5 dBm, the mixer achieves a conversion gain of -12.5 dB. The RF port frequency bandwidth is from 35 to 45 GHz. The isolation from LO port to RF port is 38 dB at 30 GHz. The input 1-dB compression power of 2 dBm with a total dc power consumption of 1 mW, and the chip size is 0.88 × 0.77 mm2. In Chapter 4, a W-band downconverter using TSMC 90 nm CMOS process. Initially, a W-band low-noise amplifier (LNA) is designed for the front-end of the circuit. However, a single transistor can only provide a gain of 2 dB in the W-band, and the cascade architecture results in excessive noise figure. Therefore, a six-stage common-source architecture is employed to increase the circuit gain and reduce the noise figure. The measured small signal gain is 13 dB and the minimum noise figure of 8 dB at 89 GHz. The total dc power consumption of the circuit is only 10 mW and the chip area of the LNA is 0.73 × 0.81 mm2. Next, the low-noise amplifier is integrated with the mixer to form a low-noise W-band downconverter. While the LO power is 5 dBm, the mixer achieves a conversion gain of 3.3 dB, the minimum noise figure is reduced to 11 dB, and the isolation from LO port to RF port is improved. The total dc power consumption of the circuit is only 15 mW, and the overall chip size is 1.4 × 0.84 mm2.
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